boards: fix Trenz TEL0025 clock and RAM size

Use the usable 25MHz CLK1_25M input on G1 as the only exposed board clock, and default the target system clock to 25MHz.

Map the TEL0025 HyperRAM window as 32MiB and refresh the generated board inventory default clock.

Author: enjoy-digital

docs/boards_inventory.md

@@ -216,7 +216,7 @@ python3 .github/scripts/generate_board_inventory.py --write
 | `trenz_te0741` | trenz_te0741 | vivado | `100000000.0` | - | included |
 | `trenz_te0890` | trenz_te0890 | vivado | `100000000.0` | - | included |
 | `trenz_tec0117` | trenz_tec0117 | gowin | `25000000.0` | SDCard, SPI SDCard | included |
-| `trenz_tel0025` | trenz_tel0025 | radiant | `50000000.0` | SDCard, SPI SDCard, SPI Flash | included |
+| `trenz_tel0025` | trenz_tel0025 | radiant | `25000000.0` | SDCard, SPI SDCard, SPI Flash | included |
 | `trenz_tem0006` | trenz_tem0006 | libero_soc | `12000000.0` | - | included |
 | `tul_pynq_z2` | tul_pynq_z2 | vivado | `100000000.0` | - | included |
 | `xilinx_ac701` | xilinx_ac701 | vivado | `100000000.0` | Ethernet, SPI Flash, PCIe | included |

litex_boards/platforms/trenz_tel0025.py

@@ -12,9 +12,7 @@
 
 _io = [
     # Clk / Rst
-    ("clk25",     0, Pins("C1"), IOStandard("LVCMOS33")), # CLK_25M.
-    ("clk25_aux", 0, Pins("G1"), IOStandard("LVCMOS33")), # CLK1_25M.
-    ("clk12",     0, Pins("E6"), IOStandard("LVCMOS33")), # CLK_12M.
+    ("clk25",      0, Pins("G1"), IOStandard("LVCMOS33")), # CLK1_25M.
     ("user_btn_n", 0, Pins("C8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
 
     # Leds (RGB LED, active-low).
@@ -153,6 +151,4 @@ def create_programmer(self, cable="ft2232"):
 
     def do_finalize(self, fragment):
         LatticeNexusPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk25",     loose=True), 1e9/25e6)
-        self.add_period_constraint(self.lookup_request("clk25_aux", loose=True), 1e9/25e6)
-        self.add_period_constraint(self.lookup_request("clk12",     loose=True), 1e9/12e6)
+        self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)

litex_boards/targets/trenz_tel0025.py

@@ -21,7 +21,7 @@
 
 # Constants ----------------------------------------------------------------------------------------
 
-_HYPERRAM_SIZE  = 8*MEGABYTE
+_HYPERRAM_SIZE  = 32*MEGABYTE
 _OPENSBI_OFFSET = 0x00f00000
 _OPENSBI_SIZE   = 0x00080000
 
@@ -60,7 +60,7 @@ def __init__(self, platform, sys_clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=50e6, toolchain="radiant",
+    def __init__(self, sys_clk_freq=25e6, toolchain="radiant",
         with_hyperram       = True,
         with_led_chaser     = True,
         with_sdcard         = False,
@@ -82,8 +82,9 @@ def __init__(self, sys_clk_freq=50e6, toolchain="radiant",
         )
         if with_opensbi and main_ram_size < (_OPENSBI_OFFSET + _OPENSBI_SIZE):
             raise ValueError(
-                "vexriscv_smp/vexiiriscv Linux variants place OpenSBI beyond "
-                "the TEL0025 8MiB HyperRAM window; use vexriscv linux instead."
+                "vexriscv_smp/vexiiriscv Linux variants place OpenSBI at "
+                "main_ram + 0x00f00000; provide at least 16MiB of main RAM "
+                "or use vexriscv linux instead."
             )
 
         # CRG --------------------------------------------------------------------------------------
@@ -136,7 +137,7 @@ def __init__(self, sys_clk_freq=50e6, toolchain="radiant",
 def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=trenz_tel0025.Platform, description="LiteX SoC on Trenz TEL0025.")
-    parser.add_target_argument("--sys-clk-freq",   default=50e6,       type=float, help="System clock frequency.")
+    parser.add_target_argument("--sys-clk-freq",   default=25e6,       type=float, help="System clock frequency.")
     parser.add_target_argument("--no-hyperram",    action="store_true",            help="Disable HyperRAM support.")
     parser.add_target_argument("--with-spi-flash", action="store_true",            help="Enable SPI Flash support.")
     parser.add_target_argument("--flash",          action="store_true",            help="Flash bitstream to SPI Flash.")