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enjoy-digitalenjoy-digital
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platforms: add more Digilent board resources
Add source-backed resources and pin fixes across Digilent platforms: Arty S7 XADC/ChipKit pins, Arty Z7 crypto/XADC correction, Genesys2 flash/OLED/I2C/USB/DisplayPort sidebands, Nexys4 sensors, Nexys Video XADC/I2C/VADJ/GTP sidebands, Zedboard video/USB pins, and Zybo audio/VGA/sideband pins. Sources: - https://github.com/Digilent/digilent-xdc/blob/master/Arty-S7-25-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Arty-S7-50-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-10-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-20-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Nexys-Video-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Zedboard-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Master.xdc - https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc
1 parent 16e0698 commit 2c89c20

7 files changed

Lines changed: 189 additions & 1 deletion

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‎litex_boards/platforms/digilent_arty_s7.py‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@
142142
"ck_io11" : "H17",
143143
"ck_io12" : "K14",
144144
"ck_io13" : "G16",
145+
"ck_ioa" : "K13",
145146

146147
# Inner Digital Header
147148
"ck_io26" : "U11",
@@ -179,6 +180,9 @@
179180
}
180181
),
181182
("XADC", {
183+
"vp_in" : "J10",
184+
"vn_in" : "K9",
185+
182186
# Outer Analog Header
183187
"vaux0_p" : "B13",
184188
"vaux0_n" : "A13",

‎litex_boards/platforms/digilent_arty_z7.py‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,9 @@
5454
IOStandard("LVCMOS33"),
5555
),
5656

57+
# Crypto
58+
("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")),
59+
5760
# Audio
5861
("audio", 0,
5962
Subsignal("pwm", Pins("R18")), # AUD_PWM.
@@ -182,7 +185,7 @@
182185
_xadc = {
183186
# Outer Analog Header
184187
"vaux1_p" : "E17",
185-
"vaux1_n" : "B18",
188+
"vaux1_n" : "D18",
186189
"vaux9_p" : "E18",
187190
"vaux9_n" : "E19",
188191
"vaux6_p" : "K14",

‎litex_boards/platforms/digilent_genesys2.py‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,18 +54,54 @@
5454

5555
# USB FIFO
5656
("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
57+
Subsignal("clko", Pins("AB27")),
5758
Subsignal("data", Pins("AD27 W27 W28 W29 Y29 Y28 AA28 AA26")),
5859
Subsignal("rxf_n", Pins("AB29")),
5960
Subsignal("txe_n", Pins("AA25")),
6061
Subsignal("rd_n", Pins("AB25")),
6162
Subsignal("wr_n", Pins("AC27")),
6263
Subsignal("siwua", Pins("AB28")),
64+
Subsignal("spien", Pins("AD29")),
6365
Subsignal("oe_n", Pins("AC30")),
6466
Misc("SLEW=FAST"),
6567
Drive(8),
6668
IOStandard("LVCMOS33"),
6769
),
6870

71+
# SPIFlash
72+
("spiflash", 0,
73+
Subsignal("cs_n", Pins("U19")),
74+
#Subsignal("clk", Pins("")), # Accessed through STARTUPE2.
75+
Subsignal("mosi", Pins("P24")),
76+
Subsignal("miso", Pins("R25")),
77+
Subsignal("wp", Pins("R20")),
78+
Subsignal("hold", Pins("R21")),
79+
IOStandard("LVCMOS33"),
80+
),
81+
("spiflash4x", 0,
82+
Subsignal("cs_n", Pins("U19")),
83+
#Subsignal("clk", Pins("")), # Accessed through STARTUPE2.
84+
Subsignal("dq", Pins("P24 R25 R20 R21")),
85+
IOStandard("LVCMOS33"),
86+
),
87+
88+
# OLED
89+
("oled", 0,
90+
Subsignal("dc", Pins("AC17"), IOStandard("LVCMOS18")),
91+
Subsignal("res", Pins("AB17"), IOStandard("LVCMOS18")),
92+
Subsignal("sclk", Pins("AF17"), IOStandard("LVCMOS18")),
93+
Subsignal("sdin", Pins("Y15"), IOStandard("LVCMOS18")),
94+
Subsignal("vbat", Pins("AB22"), IOStandard("LVCMOS33")),
95+
Subsignal("vdd", Pins("AG17"), IOStandard("LVCMOS18")),
96+
),
97+
98+
# I2C
99+
("i2c", 0,
100+
Subsignal("scl", Pins("AE30")),
101+
Subsignal("sda", Pins("AF30")),
102+
IOStandard("LVCMOS33"),
103+
),
104+
69105
# SDCard
70106
("spisdcard", 0,
71107
Subsignal("rst", Pins("AE24")),
@@ -128,6 +164,7 @@
128164
("eth", 0,
129165
Subsignal("rst_n", Pins("AH24"), IOStandard("LVCMOS33")),
130166
Subsignal("int_n", Pins("AK16"), IOStandard("LVCMOS18")),
167+
Subsignal("pme_n", Pins("AK15"), IOStandard("LVCMOS18")),
131168
Subsignal("mdio", Pins("AG12"), IOStandard("LVCMOS15")),
132169
Subsignal("mdc", Pins("AF12"), IOStandard("LVCMOS15")),
133170
Subsignal("rx_ctl", Pins("AH11"), IOStandard("LVCMOS15")),
@@ -168,6 +205,34 @@
168205
Subsignal("hpa", Pins("AH29"), IOStandard("LVCMOS33")),
169206
),
170207

208+
# USB OTG
209+
("usb_otg", 0,
210+
Subsignal("clk", Pins("AD18")),
211+
Subsignal("data", Pins("AE14 AE15 AC15 AC16 AB15 AA15 AD14 AC14")),
212+
Subsignal("dir", Pins("Y16")),
213+
Subsignal("nxt", Pins("AA16")),
214+
Subsignal("reset_n", Pins("AB14")),
215+
Subsignal("stp", Pins("AA17")),
216+
Subsignal("vbusoc", Pins("AF16")),
217+
IOStandard("LVCMOS18"),
218+
),
219+
220+
# DisplayPort
221+
("displayport_in", 0,
222+
Subsignal("aux_in_n", Pins("AC19"), IOStandard("LVCMOS18")),
223+
Subsignal("aux_in_p", Pins("AB19"), IOStandard("LVCMOS18")),
224+
Subsignal("aux_out_n", Pins("Y18"), IOStandard("LVCMOS18")),
225+
Subsignal("aux_out_p", Pins("Y19"), IOStandard("LVCMOS18")),
226+
Subsignal("hpd", Pins("AE21"), IOStandard("LVCMOS33")),
227+
),
228+
("displayport_out", 0,
229+
Subsignal("aux_in_n", Pins("AD16"), IOStandard("LVCMOS18")),
230+
Subsignal("aux_in_p", Pins("AD17"), IOStandard("LVCMOS18")),
231+
Subsignal("aux_out_n", Pins("AB18"), IOStandard("LVCMOS18")),
232+
Subsignal("aux_out_p", Pins("AA18"), IOStandard("LVCMOS18")),
233+
Subsignal("hpd", Pins("AD21"), IOStandard("LVCMOS33")),
234+
),
235+
171236
# VGA
172237
("vga", 0,
173238
Subsignal("r", Pins("AK25 AG25 AH25 AK24 AJ24")),

‎litex_boards/platforms/digilent_nexys4.py‎

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Original file line numberDiff line numberDiff line change
@@ -203,6 +203,33 @@
203203
IOStandard("LVCMOS33"),
204204
Misc("PULLUP True"),
205205
),
206+
207+
# Accelerometer
208+
("accelerometer", 0,
209+
Subsignal("cs_n", Pins("C15")),
210+
Subsignal("clk", Pins("D15")),
211+
Subsignal("mosi", Pins("B14")),
212+
Subsignal("miso", Pins("D13")),
213+
Subsignal("int", Pins("C16 E15"), Misc("PULLUP True")),
214+
IOStandard("LVCMOS33"),
215+
),
216+
217+
# Temperature Sensor
218+
("temp_sensor", 0,
219+
Subsignal("scl", Pins("F16")),
220+
Subsignal("sda", Pins("G16")),
221+
Subsignal("int", Pins("D14"), Misc("PULLUP True")),
222+
Subsignal("ct", Pins("C14"), Misc("PULLUP True")),
223+
IOStandard("LVCMOS33"),
224+
),
225+
226+
# Microphone
227+
("microphone", 0,
228+
Subsignal("clk", Pins("J5")),
229+
Subsignal("data", Pins("H5")),
230+
Subsignal("lr_sel", Pins("F5")),
231+
IOStandard("LVCMOS33"),
232+
),
206233
]
207234

208235
# Connectors ---------------------------------------------------------------------------------------

‎litex_boards/platforms/digilent_nexys_video.py‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,12 +63,14 @@
6363

6464
# USB FIFO
6565
("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
66+
Subsignal("clko", Pins("Y18")),
6667
Subsignal("data", Pins("U20 P14 P15 U17 R17 P16 R18 N14")),
6768
Subsignal("rxf_n", Pins("N17")),
6869
Subsignal("txe_n", Pins("Y19")),
6970
Subsignal("rd_n", Pins("P19")),
7071
Subsignal("wr_n", Pins("R19")),
7172
Subsignal("siwua", Pins("P17")),
73+
Subsignal("spien", Pins("R14")),
7274
Subsignal("oe_n", Pins("V17")),
7375
Misc("SLEW=FAST"),
7476
Drive(8),
@@ -131,6 +133,7 @@
131133
("eth", 0,
132134
Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")),
133135
Subsignal("int_n", Pins("Y14")),
136+
Subsignal("pme_n", Pins("W14")),
134137
Subsignal("mdio", Pins("Y16")),
135138
Subsignal("mdc", Pins("AA16")),
136139
Subsignal("rx_ctl", Pins("W10")),
@@ -202,6 +205,20 @@
202205

203206
# Others
204207
("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
208+
("vadj_en", 0, Pins("V14"), IOStandard("LVCMOS25")),
209+
210+
# I2C
211+
("i2c", 0,
212+
Subsignal("scl", Pins("W5")),
213+
Subsignal("sda", Pins("V5")),
214+
IOStandard("LVCMOS33"),
215+
),
216+
217+
# GTP RefClk
218+
("gtp_refclk", 0,
219+
Subsignal("p", Pins("F6")),
220+
Subsignal("n", Pins("E6")),
221+
),
205222

206223
# PS/2
207224
("ps2", 0,
@@ -224,6 +241,16 @@
224241
("pmoda", "AB22 AB21 AB20 AB18 Y21 AA21 AA20 AA18"),
225242
("pmodb", "V9 V8 V7 W7 W9 Y9 Y8 Y7"),
226243
("pmodc", "Y6 AA6 AA8 AB8 R6 T6 AB7 AB6"),
244+
("XADC", {
245+
"vaux1_p" : "J14",
246+
"vaux1_n" : "H14",
247+
"vaux0_p" : "H13",
248+
"vaux0_n" : "G13",
249+
"vaux8_p" : "G15",
250+
"vaux8_n" : "G16",
251+
"vaux9_p" : "J15",
252+
"vaux9_n" : "H15",
253+
}),
227254
("LPC", {
228255
"DP0_C2M_P" : "D7",
229256
"DP0_C2M_N" : "C7",

‎litex_boards/platforms/digilent_zedboard.py‎

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Original file line numberDiff line numberDiff line change
@@ -66,6 +66,43 @@
6666
),
6767
("audio_addr", 0, Pins("AB1 Y5"), IOStandard("LVCMOS33")),
6868

69+
# HDMI
70+
("hdmi", 0,
71+
Subsignal("clk", Pins("W18")),
72+
Subsignal("d", Pins(
73+
"Y13 AA13 AA14 Y14 AB15 AB16 AA16 AB17",
74+
"AA17 Y15 W13 W15 V15 U17 V14 V13")),
75+
Subsignal("de", Pins("U16")),
76+
Subsignal("hsync", Pins("V17")),
77+
Subsignal("vsync", Pins("W17")),
78+
Subsignal("int", Pins("W16")),
79+
Subsignal("scl", Pins("AA18")),
80+
Subsignal("sda", Pins("Y16")),
81+
Subsignal("spdif", Pins("U15")),
82+
Subsignal("spdif_out", Pins("Y18")),
83+
IOStandard("LVCMOS33"),
84+
),
85+
86+
# VGA
87+
("vga", 0,
88+
Subsignal("r", Pins("V20 U20 V19 V18")),
89+
Subsignal("g", Pins("AB22 AA22 AB21 AA21")),
90+
Subsignal("b", Pins("Y21 Y20 AB20 AB19")),
91+
Subsignal("hs", Pins("AA19")),
92+
Subsignal("vs", Pins("Y19")),
93+
IOStandard("LVCMOS33"),
94+
),
95+
96+
# USB OTG
97+
("usb_otg", 0,
98+
Subsignal("reset_n", Pins("G17")),
99+
Subsignal("vbusoc", Pins("L16")),
100+
IOStandard("LVCMOS33"),
101+
),
102+
103+
# Misc
104+
("pudc_b", 0, Pins("K16"), IOStandard("LVCMOS33")),
105+
69106
# PS7
70107
("ps7_clk", 0, Pins("F7")),
71108
("ps7_porb", 0, Pins("B5")),

‎litex_boards/platforms/digilent_zybo_z7.py‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@
7676
("audio_i2s", 0,
7777
Subsignal("clk", Pins("R19")),
7878
Subsignal("sync", Pins("T19")),
79+
Subsignal("sync_adc", Pins("Y18")),
7980
Subsignal("sd_adc", Pins("R16")),
8081
Subsignal("sd_dac", Pins("R18")),
8182
IOStandard("LVCMOS33"),
@@ -164,12 +165,36 @@
164165
("audio_i2s", 0,
165166
Subsignal("clk", Pins("K18")),
166167
Subsignal("sync", Pins("L17")),
168+
Subsignal("sync_adc", Pins("M18")),
167169
Subsignal("sd_adc", Pins("K17")),
168170
Subsignal("sd_dac", Pins("M17")),
169171
IOStandard("LVCMOS33"),
170172
),
171173
("audio_clk", 0, Pins("T19"), IOStandard("LVCMOS33")),
172174

175+
# Ethernet PHY sideband
176+
("eth_phy", 0,
177+
Subsignal("int_n", Pins("F16")),
178+
Subsignal("rst_n", Pins("E17")),
179+
IOStandard("LVCMOS33"),
180+
),
181+
182+
# USB OTG
183+
("usb_otg", 0,
184+
Subsignal("oc", Pins("U13")),
185+
IOStandard("LVCMOS33"),
186+
),
187+
188+
# VGA
189+
("vga", 0,
190+
Subsignal("r", Pins("M19 L20 J20 G20 F19")),
191+
Subsignal("g", Pins("H18 N20 L19 J19 H20 F20")),
192+
Subsignal("b", Pins("P20 M20 K19 J18 G19")),
193+
Subsignal("hs", Pins("P19")),
194+
Subsignal("vs", Pins("R19")),
195+
IOStandard("LVCMOS33"),
196+
),
197+
173198
("hdmi_out_en", 0, Pins("F17"), IOStandard("LVCMOS33")),
174199
]
175200

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