platforms/targets: align qmtech kintex parser integration with common pattern

Author: enjoy-digital

litex_boards/platforms/qmtech_kintex7_devboard.py

@@ -8,7 +8,7 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
-from litex.build.xilinx import XilinxPlatform
+from litex.build.xilinx import Xilinx7SeriesPlatform
 from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
@@ -141,7 +141,7 @@
 
 # Platform -----------------------------------------------------------------------------------------
 
-class Platform(XilinxPlatform):
+class Platform(Xilinx7SeriesPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
 
@@ -150,7 +150,7 @@ def __init__(self, toolchain="vivado"):
         io = _io
         connectors = _connectors
 
-        XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
+        Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
 
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
@@ -167,5 +167,5 @@ def create_programmer(self):
 
 
     def do_finalize(self, fragment):
-        XilinxPlatform.do_finalize(self, fragment)
+        Xilinx7SeriesPlatform.do_finalize(self, fragment)
         self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

litex_boards/platforms/qmtech_xc7k325t.py

@@ -7,7 +7,7 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
-from litex.build.xilinx import XilinxPlatform
+from litex.build.xilinx import Xilinx7SeriesPlatform
 from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
@@ -137,7 +137,7 @@
 
 # Platform -----------------------------------------------------------------------------------------
 
-class Platform(XilinxPlatform):
+class Platform(Xilinx7SeriesPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
 
@@ -165,7 +165,7 @@ def __init__(self, toolchain="vivado", with_daughterboard=False, with_core_resou
         elif with_core_resources:
             io += self.core_resources_standalone
 
-        XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
+        Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
 
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
@@ -183,5 +183,5 @@ def create_programmer(self):
 
 
     def do_finalize(self, fragment):
-        XilinxPlatform.do_finalize(self, fragment)
+        Xilinx7SeriesPlatform.do_finalize(self, fragment)
         self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

litex_boards/targets/opensourcesdrlab_kintex7.py

@@ -11,7 +11,6 @@
 from migen import *
 
 from litex_boards.platforms import opensourcesdrlab_kintex7
-from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import SoCRegion
@@ -103,18 +102,12 @@ def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(description="LiteX SoC on Open Source SDR Lab Kintex-7.")
-    parser.add_target_argument("--toolchain",    default="vivado",          help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
-    parser.add_target_argument("--build",        action="store_true",       help="Build bitstream.")
-    parser.add_target_argument("--load",         action="store_true",       help="Load bitstream.")
+    parser = LiteXArgumentParser(platform=opensourcesdrlab_kintex7.Platform, description="LiteX SoC on Open Source SDR Lab Kintex-7.")
     parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
 
     parser.add_target_argument("--with-pcie",       action="store_true", help="Enable PCIe support.")
     parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     parser.add_target_argument("--with-spi-flash",  action="store_true", help="Enable memory-mapped SPI flash.")
-    builder_args(parser)
-    soc_core_args(parser)
-    vivado_build_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
@@ -123,17 +116,16 @@ def main():
         with_spi_flash  = args.with_spi_flash,
         with_pcie       = args.with_pcie,
         with_spi_sdcard = args.with_spi_sdcard,
-        **soc_core_argdict(args)
+        **parser.soc_argdict
     )
 
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
 
-    builder = Builder(soc, **builder_argdict(args))
+    builder = Builder(soc, **parser.builder_argdict)
 
-    builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
     if args.build:
-        builder.build(**builder_kwargs)
+        builder.build(**parser.toolchain_argdict)
 
     if args.load:
         prog = soc.platform.create_programmer()

litex_boards/targets/qmtech_kintex7_devboard.py

@@ -12,7 +12,6 @@
 from migen import *
 
 from litex_boards.platforms import qmtech_kintex7_devboard
-from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import SoCRegion
@@ -138,10 +137,7 @@ def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6),
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(description="LiteX SoC on QMTech Kintex-7 Devboard.")
-    parser.add_target_argument("--toolchain",    default="vivado",          help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
-    parser.add_target_argument("--build",        action="store_true",       help="Build bitstream.")
-    parser.add_target_argument("--load",         action="store_true",       help="Load bitstream.")
+    parser = LiteXArgumentParser(platform=qmtech_kintex7_devboard.Platform, description="LiteX SoC on QMTech Kintex-7 Devboard.")
     parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support.")
@@ -160,9 +156,6 @@ def main():
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
     viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
     viopts.add_argument("--with-video-colorbars",   action="store_true", help="Enable Video Colorbars (VGA).")
-    builder_args(parser)
-    soc_core_args(parser)
-    vivado_build_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
@@ -178,15 +171,15 @@ def main():
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
         with_video_colorbars   = args.with_video_colorbars,
-        **soc_core_argdict(args)
+        **parser.soc_argdict
     )
 
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
     if args.with_sdcard:
         soc.add_sdcard()
 
-    builder = Builder(soc, **builder_argdict(args))
+    builder = Builder(soc, **parser.builder_argdict)
     if args.with_ethernet or args.with_etherbone:
         os.makedirs(os.path.join(builder.software_dir, "include/generated"),
                     exist_ok=True)
@@ -195,9 +188,8 @@ def main():
             "// Force 100Base-T speed\n"
             "#define TARGET_ETHPHY_INIT_FUNC() mdio_write(0, 0, 0x2100)")
 
-    builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
     if args.build:
-        builder.build(**builder_kwargs)
+        builder.build(**parser.toolchain_argdict)
 
     if args.load:
         prog = soc.platform.create_programmer()

litex_boards/targets/qmtech_xc7k325t.py

@@ -11,7 +11,6 @@
 from migen import *
 
 from litex_boards.platforms import qmtech_xc7k325t
-from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import SoCRegion
@@ -144,10 +143,7 @@ def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboa
 
 def main():
     from litex.build.parser import LiteXArgumentParser
-    parser = LiteXArgumentParser(description="LiteX SoC on QMTech XC7K325T")
-    parser.add_target_argument("--toolchain",          default="vivado",          help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
-    parser.add_target_argument("--build",              action="store_true",       help="Build bitstream.")
-    parser.add_target_argument("--load",               action="store_true",       help="Load bitstream.")
+    parser = LiteXArgumentParser(platform=qmtech_xc7k325t.Platform, description="LiteX SoC on QMTech XC7K325T")
     parser.add_target_argument("--sys-clk-freq",       default=100e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--with-daughterboard", action="store_true",       help="Board plugged into the QMTech daughterboard.")
     ethopts = parser.target_group.add_mutually_exclusive_group()
@@ -167,9 +163,6 @@ def main():
     viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (VGA).")
     viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
     viopts.add_argument("--with-video-colorbars",   action="store_true", help="Enable Video Colorbars (VGA).")
-    builder_args(parser)
-    soc_core_args(parser)
-    vivado_build_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
@@ -186,15 +179,15 @@ def main():
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,
         with_video_colorbars   = args.with_video_colorbars,
-        **soc_core_argdict(args)
+        **parser.soc_argdict
     )
 
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
     if args.with_sdcard:
         soc.add_sdcard()
 
-    builder = Builder(soc, **builder_argdict(args))
+    builder = Builder(soc, **parser.builder_argdict)
     if args.with_ethernet or args.with_etherbone:
         os.makedirs(os.path.join(builder.software_dir, "include/generated"),
                     exist_ok=True)
@@ -203,9 +196,8 @@ def main():
             "// Force 100Base-T speed\n"
             "#define TARGET_ETHPHY_INIT_FUNC() mdio_write(0, 0, 0x2100)")
 
-    builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
     if args.build:
-        builder.build(**builder_kwargs)
+        builder.build(**parser.toolchain_argdict)
 
     if args.load:
         prog = soc.platform.create_programmer()