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Marco Tassemeier
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Initial support for Xilinx KCU116
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‎litex_boards/platforms/xilinx_kcu116.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Marco Tassemeier <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk300", 0,
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Subsignal("p", Pins("K22"), IOStandard("DIFF_SSTL12")),
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Subsignal("n", Pins("K23"), IOStandard("DIFF_SSTL12"))
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),
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("clk125", 0,
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Subsignal("p", Pins("G12"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("F12"), IOStandard("LVDS_25"))
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),
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("FPGA_EMCCLK", 0, Pins("N21"), IOStandard("LVCMOS18")),
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("USER_MGT_CLK", 0,
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Subsignal("p", Pins("M7")),
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Subsignal("n", Pins("M6"))
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),
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("CLK_74_25", 0,
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Subsignal("p", Pins("D11"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("D10"), IOStandard("LVDS_25"))
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),
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("cpu_reset", 0, Pins("B9"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("C9"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D9"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("E10"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("E11"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("F9"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("F10"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("G9"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("G10"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn_c", 0, Pins("A9"), IOStandard("LVCMOS33")),
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("user_btn_n", 0, Pins("A10"), IOStandard("LVCMOS33")),
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("user_btn_s", 0, Pins("C11"), IOStandard("LVCMOS33")),
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("user_btn_w", 0, Pins("B10"), IOStandard("LVCMOS33")),
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("user_btn_e", 0, Pins("B11"), IOStandard("LVCMOS33")),
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# DIP-Switches
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("user_dip_sw", 0, Pins("G11"), IOStandard("LVCMOS33")),
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("user_dip_sw", 1, Pins("H11"), IOStandard("LVCMOS33")),
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("user_dip_sw", 2, Pins("H9"), IOStandard("LVCMOS33")),
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("user_dip_sw", 3, Pins("J9"), IOStandard("LVCMOS33")),
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# SMA
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("user_sma_clock", 0,
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Subsignal("p", Pins("J23"), IOStandard("DIFF_SSTL12")),
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Subsignal("n", Pins("J24"), IOStandard("DIFF_SSTL12"))
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),
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("user_sma_gpio", 0,
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Subsignal("p", Pins("K25"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("n", Pins("K26"), IOStandard("DIFF_SSTL12_DCI"))
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("AE13")),
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Subsignal("sda", Pins("AF13")),
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IOStandard("LVCMOS33")
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),
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("i2c_hdmi", 0,
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Subsignal("scl", Pins("AD15")),
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Subsignal("sda", Pins("AE15")),
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IOStandard("LVCMOS33")
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),
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# Serial
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("serial", 0,
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Subsignal("cts", Pins("Y13")),
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Subsignal("rts", Pins("AA13")),
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Subsignal("tx", Pins("W13")),
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Subsignal("rx", Pins("W12")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0, # clock needs to be accessed through primitive
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Subsignal("cs_n"), Pins("AA12"),
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Subsignal("dq"), Pins("AD11 AC12 AC11 AE11"),
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IOStandard("LVCMOS18")
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),
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("spiflash", 1, # clock needs to be accessed through primitive
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Subsignal("cs_n"), Pins("U22"),
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Subsignal("dq"), Pins("N23 P23 R20 R21"),
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IOStandard("LVCMOS18")
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),
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# HDMI
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("hdmi", 0,
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Subsignal("d", Pins(
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"V21 V22 T22 T23 W19 W20 Y22 Y23",
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"Y25 Y26 AA24 AA25 W25 W26 V23 W23",
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"V24 W24")),
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Subsignal("de", Pins("U20")),
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Subsignal("clk", Pins("P20")),
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Subsignal("vsync", Pins("U21")),
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Subsignal("hsync", Pins("V19")),
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Subsignal("spdif", Pins("T20")),
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Subsignal("spdif_out", Pins("U19")),
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IOStandard("LVCMOS18")
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),
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"D25 D23 D26 D24 E26 C26 G22 B25",
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"F22 C24 E25 F23 E23 B26"),
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IOStandard("SSTL12")),
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Subsignal("ba", Pins("H22 H21"), IOStandard("SSTL12")),
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Subsignal("bg", Pins("G26"), IOStandard("SSTL12")),
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Subsignal("ras_n", Pins("F24"), IOStandard("SSTL12")), # A16
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Subsignal("cas_n", Pins("F25"), IOStandard("SSTL12")), # A15
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Subsignal("we_n", Pins("H26"), IOStandard("SSTL12")), # A14
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Subsignal("cs_n", Pins("H23"), IOStandard("SSTL12")),
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Subsignal("act_n", Pins("J26"), IOStandard("SSTL12")),
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#Subsignal("ten", Pins(""), IOStandard("SSTL12")),
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Subsignal("alert_n", Pins("L24"), IOStandard("SSTL12")),
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Subsignal("par", Pins("J25"), IOStandard("SSTL12")),
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Subsignal("dm", Pins("A22 C18 H18 G15"), IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"C22 B24 C23 A24 D21 B22 E21 A25",
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"A19 C17 A20 B17 B20 A15 B19 B15",
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"F18 G21 F19 D20 E18 D19 G20 D18",
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"H17 D16 G16 D15 E15 C16 H16 G17"),
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IOStandard("POD12_DCI")),
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Subsignal("dqs_p", Pins("C21 A17 F20 E16"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_n", Pins("B21 A18 E20 E17"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("clk_p", Pins("G24"), IOStandard("DIFF_POD12")),
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Subsignal("clk_n", Pins("G25"), IOStandard("DIFF_POD12")),
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Subsignal("cke", Pins("M24"), IOStandard("SSTL12")),
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Subsignal("odt", Pins("H24"), IOStandard("SSTL12")),
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Subsignal("reset_n", Pins("L25"), IOStandard("LVCMOS12")),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("T19"), IOStandard("LVCMOS18")),
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Subsignal("wake_n", Pins("P19"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("V7")),
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Subsignal("clk_n", Pins("V6")),
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Subsignal("rx_p", Pins("P2")),
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Subsignal("rx_n", Pins("P1")),
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Subsignal("tx_p", Pins("R5")),
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Subsignal("tx_n", Pins("R4"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("T19"), IOStandard("LVCMOS18")),
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Subsignal("wake_n", Pins("P19"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("V7")),
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Subsignal("clk_n", Pins("V6")),
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Subsignal("rx_p", Pins("P2 T2 V2 Y2")),
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Subsignal("rx_n", Pins("P1 T1 V1 Y1")),
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Subsignal("tx_p", Pins("R5 U5 W5 AA5")),
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Subsignal("tx_n", Pins("R4 U4 W4 AA4"))
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),
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("pcie_x8", 0,
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Subsignal("rst_n", Pins("T19"), IOStandard("LVCMOS18")),
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Subsignal("wake_n", Pins("P19"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("V7")),
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Subsignal("clk_n", Pins("V6")),
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Subsignal("rx_p", Pins("P2 T2 V2 Y2 AB2 AD2 AE4 AF2")),
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Subsignal("rx_n", Pins("P1 T1 V1 Y1 AB1 AD1 AE3 AF1")),
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Subsignal("tx_p", Pins("R5 U5 W5 AA5 AC5 AD7 AE9 AF7")),
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Subsignal("tx_n", Pins("R4 U4 W4 AA4 AC4 AD6 AE8 AF6"))
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),
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# SFP
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("sfp", 0,
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Subsignal("txp", Pins("N5")),
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Subsignal("txn", Pins("N4")),
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Subsignal("rxp", Pins("M2")),
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Subsignal("rxn", Pins("M1"))
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),
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("sfp_tx", 0,
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Subsignal("p", Pins("N5")),
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Subsignal("n", Pins("N4")),
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("M2")),
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Subsignal("n", Pins("M1")),
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),
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("sfp_tx_disable_n", 0, Pins("AB14"), IOStandard("LVCMOS33")),
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("sfp", 1,
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Subsignal("txp", Pins("L5")),
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Subsignal("txn", Pins("L4")),
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Subsignal("rxp", Pins("K2")),
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Subsignal("rxn", Pins("K1"))
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),
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("sfp_tx", 1,
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Subsignal("p", Pins("L5")),
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Subsignal("n", Pins("L4")),
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),
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("sfp_rx", 1,
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Subsignal("p", Pins("K2")),
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Subsignal("n", Pins("K1")),
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),
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("sfp_tx_disable_n", 1, Pins("AA14"), IOStandard("LVCMOS33")),
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("sfp", 2,
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Subsignal("txp", Pins("J5")),
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Subsignal("txn", Pins("J4")),
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Subsignal("rxp", Pins("H2")),
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Subsignal("rxn", Pins("H1"))
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),
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("sfp_tx", 2,
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Subsignal("p", Pins("J5")),
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Subsignal("n", Pins("J4")),
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),
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("sfp_rx", 2,
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Subsignal("p", Pins("H2")),
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Subsignal("n", Pins("H1")),
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),
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("sfp_tx_disable_n", 2, Pins("AA15"), IOStandard("LVCMOS33")),
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("sfp", 3,
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Subsignal("txp", Pins("G5")),
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Subsignal("txn", Pins("G4")),
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Subsignal("rxp", Pins("F2")),
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Subsignal("rxn", Pins("F1"))
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),
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("sfp_tx", 3,
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Subsignal("p", Pins("G5")),
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Subsignal("n", Pins("G4")),
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),
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("sfp_rx", 3,
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Subsignal("p", Pins("F2")),
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Subsignal("n", Pins("F1")),
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),
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("sfp_tx_disable_n", 3, Pins("Y15"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("HPC", {
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"DP0_C2M_P" : "F7",
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"DP0_C2M_N" : "F6",
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"DP0_M2C_P" : "D2",
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"DP0_M2C_N" : "D1",
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"DP1_C2M_P" : "E5",
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"DP1_C2M_N" : "E4",
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"DP1_M2C_P" : "C4",
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"DP1_M2C_N" : "C3",
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"DP2_C2M_P" : "D7",
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"DP2_C2M_N" : "D6",
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"DP2_M2C_P" : "B2",
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"DP2_M2C_N" : "B1",
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"DP3_C2M_P" : "B7",
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"DP3_C2M_N" : "B6",
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"DP3_M2C_P" : "A4",
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"DP3_M2C_N" : "A3",
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"LA00_P_CC" : "AD20", # LVDS
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"LA00_N_CC" : "AE20", # LVDS
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"LA01_P_CC" : "AC19", # LVDS
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"LA01_N_CC" : "AD19", # LVDS
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"LA02_P" : "Y17", # LVDS
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"LA02_N" : "AA17", # LVDS
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"LA03_P" : "AB17", # LVDS
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"LA03_N" : "AC17", # LVDS
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"LA04_P" : "AA20", # LVDS
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"LA04_N" : "AB20", # LVDS
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"LA05_P" : "AA19", # LVDS
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"LA05_N" : "AB19", # LVDS
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"LA06_P" : "Y20", # LVDS
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"LA06_N" : "Y21", # LVDS
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"LA07_P" : "AD16", # LVDS
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"LA07_N" : "AE16", # LVDS
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"LA08_P" : "AE17", # LVDS
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"LA08_N" : "AF17", # LVDS
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"LA09_P" : "AC18", # LVDS
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"LA09_N" : "AD18", # LVDS
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"LA10_P" : "AF18", # LVDS
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"LA10_N" : "AF19", # LVDS
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"LA11_P" : "Y18", # LVDS
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"LA11_N" : "AA18", # LVDS
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"LA12_P" : "AC22", # LVDS
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"LA12_N" : "AC23", # LVDS
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"LA13_P" : "AD23", # LVDS
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"LA13_N" : "AE23", # LVDS
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"LA14_P" : "AE22", # LVDS
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"LA14_N" : "AF22", # LVDS
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"LA15_P" : "AB24", # LVDS
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"LA15_N" : "AC24", # LVDS
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"LA16_P" : "AD24", # LVDS
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"LA16_N" : "AD25", # LVDS
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"LA17_P_CC" : "AD21", # LVDS
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"LA17_N_CC" : "AE21", # LVDS
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"LA18_P_CC" : "AA22", # LVDS
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"LA18_N_CC" : "AB22", # LVDS
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"LA19_P" : "AC26", # LVDS
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"LA19_N" : "AD26", # LVDS
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"LA20_P" : "AF24", # LVDS
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"LA20_N" : "AF25", # LVDS
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"LA21_P" : "AB25", # LVDS
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"LA21_N" : "AB26", # LVDS
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"LA22_P" : "AE25", # LVDS
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"LA22_N" : "AE26", # LVDS
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"GBTCLK0_M2C_P" : "K7",
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"GBTCLK0_M2C_N" : "K6",
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"GBTCLK1_M2C_P" : "H7",
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"GBTCLK1_M2C_N" : "H6",
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"CLK0_M2C_P" : "AB21", # LVDS
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"CLK0_M2C_N" : "AC21", # LVDS
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"PG_M2C" : "H13" # LVCMOS33
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}),
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("pmod0", "A14 B15 A12 A13 B12 C12 C13 C14"), # LVCMOS33
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("pmod1", "D13 D14 E12 E13 F13 F14 J14 J15") # LVCMOS33
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPlatform.__init__(self, "xcku5p-ffvb676-2-e", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxUSPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("FPGA_EMCCLK", loose=True), 1e9/90e6)
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self.add_period_constraint(self.lookup_request("CLK_74_25", loose=True), 1e9/74.25e6)
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# DDR4 memory Internal Vref
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]")

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