platforms/sqrl_fk33: fix clk200_n pin and PCIe refclk polarity

Restore the original (pre-71cd0f01) assignments, validated against
Vivado 2024.1 package/site data on xcvu33p-fsvh2104:

- clk200_n: AY23 is not a valid package pin on this device (Vivado
  CRITICAL WARNING Common 17-69); BC26's differential partner is BC27.
- PCIe refclk: AD9 is the IOBM (positive) site and AD8 the IOBS
  (negative) site, so clk_p = AD9 / clk_n = AD8 on all pcie_x*
  resources. The swapped assignment is rejected with Vivado 12-1411
  (positive port of a differential pair cannot be placed on a negative
  package pin), leaving the refclk unconstrained and failing bitstream
  DRC UCIO-1.

Verified with a full --with-hbm --with-pcie bitstream build (timing
met, bitstream DRC clean).

Author: enjoy-digital

litex_boards/platforms/sqrl_fk33.py

@@ -16,7 +16,7 @@
     # Clk / Rst
     ("clk200", 0,
         Subsignal("p", Pins("BC26"), IOStandard("LVDS")),
-        Subsignal("n", Pins("AY23"), IOStandard("LVDS"))
+        Subsignal("n", Pins("BC27"), IOStandard("LVDS"))
     ),
 
     # Leds
@@ -49,8 +49,8 @@
     # PCIe
     ("pcie_x2", 0,
         Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")),
-        Subsignal("clk_p", Pins("AD8")),
-        Subsignal("clk_n", Pins("AD9")),
+        Subsignal("clk_p", Pins("AD9")),
+        Subsignal("clk_n", Pins("AD8")),
         Subsignal("rx_p",  Pins("AL2 AM4")),
         Subsignal("rx_n",  Pins("AL1 AM3")),
         Subsignal("tx_p",  Pins("Y5  AA7")),
@@ -59,8 +59,8 @@
 
     ("pcie_x4", 0,
         Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")),
-        Subsignal("clk_p", Pins("AD8")),
-        Subsignal("clk_n", Pins("AD9")),
+        Subsignal("clk_p", Pins("AD9")),
+        Subsignal("clk_n", Pins("AD8")),
         Subsignal("rx_p",  Pins("AL2 AM4 AK4 AN2")),
         Subsignal("rx_n",  Pins("AL1 AM3 AK3 AN1")),
         Subsignal("tx_p",  Pins("Y5  AA7 AB5 AC7")),
@@ -69,8 +69,8 @@
 
     ("pcie_x8", 0,
         Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")),
-        Subsignal("clk_p", Pins("AD8")),
-        Subsignal("clk_n", Pins("AD9")),
+        Subsignal("clk_p", Pins("AD9")),
+        Subsignal("clk_n", Pins("AD8")),
         Subsignal("rx_p",  Pins("AL2 AM4 AK4 AN2 AP4 AR2 AT4 AU2")),
         Subsignal("rx_n",  Pins("AL1 AM3 AK3 AN1 AP3 AR1 AT3 AU1")),
         Subsignal("tx_p",  Pins("Y5  AA7 AB5 AC7 AD5 AF5 AE7 AH5")),
@@ -79,8 +79,8 @@
 
     ("pcie_x16", 0,
         Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")),
-        Subsignal("clk_p", Pins("AD8")),
-        Subsignal("clk_n", Pins("AD9")),
+        Subsignal("clk_p", Pins("AD9")),
+        Subsignal("clk_n", Pins("AD8")),
         Subsignal("rx_p",  Pins("AL2 AM4 AK4 AN2 AP4 AR2 AT4 AU2 AV4 AW2 BA2 BC2 AY4 BB4 BD4 BE6")),
         Subsignal("rx_n",  Pins("AL1 AM3 AK3 AN1 AP3 AR1 AT3 AU1 AV3 AW1 BA1 BC1 AY3 BB3 BD3 BE5")),
         Subsignal("tx_p",  Pins("Y5  AA7 AB5 AC7 AD5 AF5 AE7 AH5 AG7 AJ7 AL7 AM9 AN7 AP9 AR7 AT9")),