Skip to content

Commit 523870b

Browse files
enjoy-digitalenjoy-digital
authored
Merge pull request #765 from litex-hub/efinix-ti375-ddr-integration
targets/efinix_ti375: use common hard DDR integration
2 parents 6ef03b4 + be632e2 commit 523870b

2 files changed

Lines changed: 48 additions & 193 deletions

File tree

‎litex_boards/platforms/efinix_ti375_c529_dev_kit.py‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -236,6 +236,27 @@
236236
),
237237
]
238238

239+
# DDR Configuration --------------------------------------------------------------------------------
240+
241+
ddr_config = {
242+
"memory_type" : "LPDDR4x",
243+
"memory_density" : "8G",
244+
"clkin_sel" : "CLKIN 0",
245+
"location" : "DDR_0",
246+
"dq_width" : 32,
247+
"physical_rank" : 1,
248+
"data_width" : 512,
249+
"address_width" : 33,
250+
"id_width" : 8,
251+
"pin_swizzle" : {
252+
"CA" : "CA[0],CA[1],CA[2],CA[3],CA[4],CA[5]",
253+
"DQM0" : "DQ[3],DQ[6],DQ[4],DQ[5],DQ[0],DQ[1],DQ[7],DQ[2],DM[0]",
254+
"DQM1" : "DQ[15],DQ[9],DQ[12],DQ[11],DQ[8],DQ[10],DQ[13],DQ[14],DM[1]",
255+
"DQM2" : "DQ[22],DQ[17],DQ[18],DQ[19],DQ[16],DQ[20],DQ[21],DQ[23],DM[2]",
256+
"DQM3" : "DQ[29],DQ[31],DQ[28],DQ[30],DQ[25],DQ[27],DQ[26],DQ[24],DM[3]",
257+
},
258+
}
259+
239260
# PMODS --------------------------------------------------------------------------------------------
240261

241262
def raw_pmod_io(pmod):
@@ -283,6 +304,8 @@ class Platform(EfinixPlatform):
283304

284305
def __init__(self, toolchain="efinity"):
285306
EfinixPlatform.__init__(self, "Ti375C529C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
307+
self.ddr_config = ddr_config
308+
self.ddr_size = 0x4000_0000 # 1GB.
286309

287310
def create_programmer(self):
288311
return EfinixProgrammer(family=self.family)

‎litex_boards/targets/efinix_ti375_c529_dev_kit.py‎

Lines changed: 25 additions & 193 deletions
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,12 @@
1616
from litex_boards.platforms import efinix_ti375_c529_dev_kit
1717

1818
from litex.soc.integration.soc import *
19-
from litex.soc.integration.soc import SoCRegion
2019
from litex.soc.integration.builder import *
2120

22-
from litex.soc.interconnect import axi
23-
2421
from litex.soc.cores.clock.efinix import *
2522
from litex.soc.cores.bitbang import I2CMaster
2623
from litex.soc.cores.pwm import PWM
24+
from litex.soc.cores.ram.efinix_ddr import EfinixDDR, add_efinix_ddr
2725

2826
from litex.soc.cores.usb_ohci import USBOHCI
2927

@@ -82,153 +80,6 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq):
8280
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
8381

8482

85-
class EfinixLPDDR4(LiteXModule):
86-
def __init__(self, soc, axi_clk):
87-
platform = soc.platform
88-
data_width = 512
89-
90-
# DRAM Blocks.
91-
# ------------------
92-
from litex.build.efinix import InterfaceWriterBlock
93-
94-
self.bus = axi_bus = axi.AXIInterface(data_width=data_width, address_width=33, id_width=8)
95-
96-
class EfinixDRAMBlock(InterfaceWriterBlock):
97-
@staticmethod
98-
def generate():
99-
name = "ddr_inst1"
100-
ddr_def = "DDR_0"
101-
clkin_sel = "CLKIN 0"
102-
data_width = "32"
103-
physical_rank = "1"
104-
mem_type = "LPDDR4x"
105-
mem_density = "8G"
106-
107-
cmd = []
108-
cmd.append('design.create_block("{}", "DDR")'.format(name))
109-
cmd.append('design.set_property("{}", "MEMORY_TYPE", "{}", "DDR")'.format(name, mem_type))
110-
cmd.append('design.set_property("{}", "DQ_WIDTH", "{}", "DDR")'.format(name, data_width))
111-
cmd.append('design.set_property("{}", "MEMORY_DENSITY", "{}", "DDR")'.format(name, mem_density))
112-
cmd.append('design.set_property("{}", "PHYSICAL_RANK", "{}", "DDR")'.format(name, physical_rank))
113-
cmd.append('design.set_property("{}", "CLKIN_SEL", "{}", "DDR")'.format(name, clkin_sel))
114-
115-
cmd.append('design.set_property("{}","TARGET0_EN", "1", "DDR")'.format(name))
116-
cmd.append('design.set_property("{}","TARGET1_EN", "0", "DDR")'.format(name))
117-
118-
cmd.append('design.set_property("{}","AXI0_ARADDR_BUS","ddr0_araddr", "DDR")'.format(name))
119-
cmd.append('design.set_property("{}","AXI0_ARAPCMD_PIN","ddr0_arapcmd", "DDR")'.format(name))
120-
cmd.append('design.set_property("{}","AXI0_ARBURST_BUS","ddr0_arburst", "DDR")'.format(name))
121-
cmd.append('design.set_property("{}","AXI0_ARID_BUS","ddr0_arid", "DDR")'.format(name))
122-
cmd.append('design.set_property("{}","AXI0_ARLEN_BUS","ddr0_arlen", "DDR")'.format(name))
123-
cmd.append('design.set_property("{}","AXI0_ARLOCK_PIN","ddr0_arlock", "DDR")'.format(name))
124-
cmd.append('design.set_property("{}","AXI0_ARQOS_PIN","ddr0_arqos", "DDR")'.format(name))
125-
cmd.append('design.set_property("{}","AXI0_ARREADY_PIN","ddr0_arready", "DDR")'.format(name))
126-
cmd.append('design.set_property("{}","AXI0_ARSIZE_BUS","ddr0_arsize", "DDR")'.format(name))
127-
cmd.append('design.set_property("{}","AXI0_ARSTN_PIN","ddr0_resetn", "DDR")'.format(name))
128-
cmd.append('design.set_property("{}","AXI0_ARVALID_PIN","ddr0_arvalid", "DDR")'.format(name))
129-
cmd.append('design.set_property("{}","AXI0_AWADDR_BUS","ddr0_awaddr", "DDR")'.format(name))
130-
cmd.append('design.set_property("{}","AXI0_AWALLSTRB_PIN","ddr0_awallstrb", "DDR")'.format(name))
131-
cmd.append('design.set_property("{}","AXI0_AWAPCMD_PIN","ddr0_awapcmd", "DDR")'.format(name))
132-
cmd.append('design.set_property("{}","AXI0_AWBURST_BUS","ddr0_awburst", "DDR")'.format(name))
133-
cmd.append('design.set_property("{}","AXI0_AWCACHE_BUS","ddr0_awcache", "DDR")'.format(name))
134-
cmd.append('design.set_property("{}","AXI0_AWCOBUF_PIN","ddr0_awcobuf", "DDR")'.format(name))
135-
cmd.append('design.set_property("{}","AXI0_AWID_BUS","ddr0_awid", "DDR")'.format(name))
136-
cmd.append('design.set_property("{}","AXI0_AWLEN_BUS","ddr0_awlen", "DDR")'.format(name))
137-
cmd.append('design.set_property("{}","AXI0_AWLOCK_PIN","ddr0_awlock", "DDR")'.format(name))
138-
cmd.append('design.set_property("{}","AXI0_AWQOS_PIN","ddr0_awqos", "DDR")'.format(name))
139-
cmd.append('design.set_property("{}","AXI0_AWREADY_PIN","ddr0_awready", "DDR")'.format(name))
140-
cmd.append('design.set_property("{}","AXI0_AWSIZE_BUS","ddr0_awsize", "DDR")'.format(name))
141-
cmd.append('design.set_property("{}","AXI0_AWVALID_PIN","ddr0_awvalid", "DDR")'.format(name))
142-
cmd.append('design.set_property("{}","AXI0_BID_BUS","ddr0_bid", "DDR")'.format(name))
143-
cmd.append('design.set_property("{}","AXI0_BREADY_PIN","ddr0_bready", "DDR")'.format(name))
144-
cmd.append('design.set_property("{}","AXI0_BRESP_BUS","ddr0_bresp", "DDR")'.format(name))
145-
cmd.append('design.set_property("{}","AXI0_BVALID_PIN","ddr0_bvalid", "DDR")'.format(name))
146-
cmd.append('design.set_property("{}","AXI0_CLK_INPUT_PIN","{}", "DDR")'.format(name, axi_clk))
147-
cmd.append('design.set_property("{}","AXI0_CLK_INVERT_EN","0", "DDR")'.format(name))
148-
cmd.append('design.set_property("{}","AXI0_DATA_WIDTH","512", "DDR")'.format(name))
149-
cmd.append('design.set_property("{}","AXI0_RDATA_BUS","ddr0_rdata", "DDR")'.format(name))
150-
cmd.append('design.set_property("{}","AXI0_RID_BUS","ddr0_rid", "DDR")'.format(name))
151-
cmd.append('design.set_property("{}","AXI0_RLAST_PIN","ddr0_rlast", "DDR")'.format(name))
152-
cmd.append('design.set_property("{}","AXI0_RREADY_PIN","ddr0_rready", "DDR")'.format(name))
153-
cmd.append('design.set_property("{}","AXI0_RRESP_BUS","ddr0_rresp", "DDR")'.format(name))
154-
cmd.append('design.set_property("{}","AXI0_RVALID_PIN","ddr0_rvalid", "DDR")'.format(name))
155-
cmd.append('design.set_property("{}","AXI0_WDATA_BUS","ddr0_wdata", "DDR")'.format(name))
156-
cmd.append('design.set_property("{}","AXI0_WLAST_PIN","ddr0_wlast", "DDR")'.format(name))
157-
cmd.append('design.set_property("{}","AXI0_WREADY_PIN","ddr0_wready", "DDR")'.format(name))
158-
cmd.append('design.set_property("{}","AXI0_WSTRB_BUS","ddr0_wstrb", "DDR")'.format(name))
159-
cmd.append('design.set_property("{}","AXI0_WVALID_PIN","ddr0_wvalid", "DDR")'.format(name))
160-
161-
cmd.append('design.set_property("{}","CFG_DONE_PIN", "cfg_done", "DDR")'.format(name))
162-
cmd.append('design.set_property("{}","CFG_RESET_PIN", "cfg_reset", "DDR")'.format(name))
163-
cmd.append('design.set_property("{}","CFG_SEL_PIN", "cfg_sel", "DDR")'.format(name))
164-
cmd.append('design.set_property("{}","CFG_START_PIN", "cfg_start", "DDR")'.format(name))
165-
166-
cmd.append('design.set_property("{}","CTRL_BUSY_PIN","", "DDR")'.format(name))
167-
cmd.append('design.set_property("{}","CTRL_CKE_PIN","", "DDR")'.format(name))
168-
cmd.append('design.set_property("{}","CTRL_CLK_INVERT_EN","0", "DDR")'.format(name))
169-
cmd.append('design.set_property("{}","CTRL_CLK_PIN","", "DDR")'.format(name))
170-
cmd.append('design.set_property("{}","CTRL_CMD_Q_ALMOST_FULL_PIN","", "DDR")'.format(name))
171-
cmd.append('design.set_property("{}","CTRL_DP_IDLE_PIN","", "DDR")'.format(name))
172-
cmd.append('design.set_property("{}","CTRL_INT_PIN","", "DDR")'.format(name))
173-
cmd.append('design.set_property("{}","CTRL_MEM_RST_VALID_PIN","", "DDR")'.format(name))
174-
cmd.append('design.set_property("{}","CTRL_PORT_BUSY_PIN","", "DDR")'.format(name))
175-
cmd.append('design.set_property("{}","CTRL_REFRESH_PIN","", "DDR")'.format(name))
176-
177-
cmd.append('design.set_property("{}","PIN_SWIZZLE_CA","CA[0],CA[1],CA[2],CA[3],CA[4],CA[5]", "DDR")'.format(name))
178-
cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM0","DQ[3],DQ[6],DQ[4],DQ[5],DQ[0],DQ[1],DQ[7],DQ[2],DM[0]", "DDR")'.format(name))
179-
cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM1","DQ[15],DQ[9],DQ[12],DQ[11],DQ[8],DQ[10],DQ[13],DQ[14],DM[1]", "DDR")'.format(name))
180-
cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM2","DQ[22],DQ[17],DQ[18],DQ[19],DQ[16],DQ[20],DQ[21],DQ[23],DM[2]", "DDR")'.format(name))
181-
cmd.append('design.set_property("{}","PIN_SWIZZLE_DQM3","DQ[29],DQ[31],DQ[28],DQ[30],DQ[25],DQ[27],DQ[26],DQ[24],DM[3]", "DDR")'.format(name))
182-
cmd.append('design.set_property("{}","PIN_SWIZZLE_EN","1", "DDR")'.format(name))
183-
184-
cmd.append('design.assign_resource("{}", "{}","DDR")\n'.format(name, ddr_def))
185-
186-
return '\n'.join(cmd) + '\n'
187-
188-
platform.toolchain.ifacewriter.blocks.append(EfinixDRAMBlock())
189-
190-
# DRAM AXI-Ports.
191-
# --------------
192-
axi_io = platform.add_iface_ios(axi_bus.get_ios("ddr0"))
193-
self.comb += axi_bus.connect_to_pads(axi_io, mode="master")
194-
195-
ios = [(f"ddr0", 0,
196-
Subsignal("arapcmd", Pins(1)),
197-
Subsignal("awallstrb", Pins(1)),
198-
Subsignal("awapcmd", Pins(1)),
199-
Subsignal("awcobuf", Pins(1)),
200-
Subsignal("resetn", Pins(1)),
201-
)]
202-
203-
io = platform.add_iface_ios(ios)
204-
self.comb += [
205-
io.arapcmd.eq(0),
206-
io.awallstrb.eq(getattr(soc.cpu, "mBus_awallStrb", 0)),
207-
io.awapcmd.eq(0),
208-
io.awcobuf.eq(0),
209-
io.resetn.eq(~ResetSignal()),
210-
]
211-
212-
cfgs = [(f"cfg", 0,
213-
Subsignal("start", Pins(1)),
214-
Subsignal("reset", Pins(1)),
215-
Subsignal("sel", Pins(1)),
216-
Subsignal("done", Pins(1)),
217-
)]
218-
219-
cfg = platform.add_iface_ios(cfgs)
220-
self.cfg_state = Signal(1, reset=0)
221-
self.cfg_count = Signal(8, reset=0)
222-
223-
self.comb += [
224-
cfg.sel.eq(0),
225-
cfg.reset.eq(self.cfg_state == 0),
226-
cfg.start.eq(self.cfg_state != 0),
227-
]
228-
229-
self.sync += self.cfg_count.eq(self.cfg_count + (self.cfg_count != 0xFF))
230-
self.sync += self.cfg_state.eq(self.cfg_state | (self.cfg_count == 0xFF))
231-
23283
# BaseSoC ------------------------------------------------------------------------------------------
23384

23485
class BaseSoC(SoCCore):
@@ -571,40 +422,18 @@ def __init__(self,
571422
for i in range(4):
572423
self.specials += DDRInput(o1=self.cpu.eth_rx_d[0+i], o2=self.cpu.eth_rx_d[4+i], i=eth.rx_data[i], clk=self.cd_eth_rx.clk)
573424

574-
# self.specials += DDROutput(i1=self.cpu.eth_rx_d[0], i2=self.cpu.eth_rx_d[4], o=debug_io.p0, clk=self.cd_eth_rx.clk)
575-
# self.specials += DDROutput(i1=self.cpu.eth_rx_d[1], i2=self.cpu.eth_rx_d[5], o=debug_io.p1, clk=self.cd_eth_rx.clk)
576-
# self.specials += DDROutput(i1=self.cpu.eth_rx_d[2], i2=self.cpu.eth_rx_d[6], o=debug_io.p2, clk=self.cd_eth_rx.clk)
577-
# self.specials += DDROutput(i1=self.cpu.eth_rx_d[3], i2=self.cpu.eth_rx_d[7], o=debug_io.p3, clk=self.cd_eth_rx.clk)
578-
# self.specials += DDROutput(i1=Signal(reset=1), i2=Signal(reset=0), o=debug_io.p4, clk=self.cd_eth_rx.clk)
579-
# self.specials += DDROutput(i1=self.cpu.eth_rx_ctl[0], i2=self.cpu.eth_rx_ctl[1], o=debug_io.p5, clk=self.cd_eth_rx.clk)
580-
581425
# LPDDR4 SDRAM -----------------------------------------------------------------------------
582426
if not self.integrated_main_ram_size:
583-
if hasattr(self.cpu, "add_memory_buses") and hasattr(self.cpu, "cpu_clk"):
584-
axi_clk = self.crg.cd_cpu.clk.name_override
585-
else:
586-
axi_clk = self.crg.cd_sys.clk.name_override
587-
588-
self.ddr = EfinixLPDDR4(self, axi_clk)
589-
axi_bus = self.ddr.bus
590-
591-
soc_region = SoCRegion(
592-
origin = self.mem_map.get("main_ram", None),
593-
size = 0x4000_0000, # 1GB.
594-
mode = "rwx",
427+
clock_domain = "cpu" if (
428+
hasattr(self.cpu, "add_memory_buses") and
429+
hasattr(self.cpu, "cpu_clk")
430+
) else "sys"
431+
self.ddr = EfinixDDR(
432+
platform = platform,
433+
clock_domain = clock_domain,
434+
**platform.ddr_config,
595435
)
596-
# Use DRAM's target0 port as Main Ram.
597-
if hasattr(self.cpu, "add_memory_buses"):
598-
self.cpu.add_memory_buses(address_width = 32, data_width = axi_bus.data_width)
599-
600-
assert len(self.cpu.memory_buses) == 1
601-
mbus = self.cpu.memory_buses[0]
602-
self.comb +=mbus.connect(axi_bus)
603-
self.bus.add_region("main_ram", soc_region)
604-
else:
605-
axi_lite_bus = axi.AXILiteInterface(data_width=axi_bus.data_width, address_width=axi_bus.address_width)
606-
self.submodules += axi.AXILite2AXI(axi_lite_bus, axi_bus)
607-
self.bus.add_slave("main_ram", axi_lite_bus, soc_region)
436+
add_efinix_ddr(self, self.ddr, size=platform.ddr_size)
608437

609438
# SPI Flash --------------------------------------------------------------------------------
610439
if with_spi_flash:
@@ -650,18 +479,21 @@ def main():
650479
eth_phy = args.eth_phy if args.eth_phy is not None else "rgmii"
651480

652481
soc = BaseSoC(
653-
sys_clk_freq = args.sys_clk_freq,
654-
cpu_clk_freq = args.cpu_clk_freq,
655-
with_ohci = args.with_ohci,
656-
with_ethernet = args.with_ethernet,
657-
with_etherbone = args.with_etherbone,
658-
with_ptp = args.with_ptp,
659-
eth_phy = eth_phy,
660-
eth_ip = args.eth_ip,
661-
eth_dynamic_ip = args.eth_dynamic_ip,
662-
ptp_p2p = args.ptp_p2p,
663-
ptp_debug = args.ptp_debug,
664-
remote_ip = args.remote_ip,
482+
sys_clk_freq = args.sys_clk_freq,
483+
cpu_clk_freq = args.cpu_clk_freq,
484+
with_spi_flash = args.with_spi_flash,
485+
spi_flash_number = args.spi_flash_number,
486+
spi_flash_rate = args.spi_flash_rate,
487+
with_ohci = args.with_ohci,
488+
with_ethernet = args.with_ethernet,
489+
with_etherbone = args.with_etherbone,
490+
with_ptp = args.with_ptp,
491+
eth_phy = eth_phy,
492+
eth_ip = args.eth_ip,
493+
eth_dynamic_ip = args.eth_dynamic_ip,
494+
ptp_p2p = args.ptp_p2p,
495+
ptp_debug = args.ptp_debug,
496+
remote_ip = args.remote_ip,
665497
**parser.soc_argdict)
666498
if args.with_spi_sdcard:
667499
soc.add_spi_sdcard()

0 commit comments

Comments
 (0)