boards: add Trenz TEL0025 support

Add a Lattice Nexus platform definition for the Trenz TEL0025 with clock, UART, LED, SPI flash, SDCard, HyperRAM, and CSI resources.

Add a board target with NXOSCA/NXPLL clocking, HyperRAM as main RAM, optional native SDCard/SPI-SD/SPI flash support, and programming hooks for SRAM load or SPI flash.

Guard against Linux CPU variants that place OpenSBI beyond the board's 8MiB HyperRAM window, while keeping the single-core VexRiscv Linux path usable for HyperRAM boot experiments.

Update the generated board inventory entry for the new target.

Author: enjoy-digital

docs/boards_inventory.md

@@ -216,6 +216,7 @@ python3 .github/scripts/generate_board_inventory.py --write
 | `trenz_te0741` | trenz_te0741 | vivado | `100000000.0` | - | included |
 | `trenz_te0890` | trenz_te0890 | vivado | `100000000.0` | - | included |
 | `trenz_tec0117` | trenz_tec0117 | gowin | `25000000.0` | SDCard, SPI SDCard | included |
+| `trenz_tel0025` | trenz_tel0025 | radiant | `50000000.0` | SDCard, SPI SDCard, SPI Flash | included |
 | `trenz_tem0006` | trenz_tem0006 | libero_soc | `12000000.0` | - | included |
 | `tul_pynq_z2` | tul_pynq_z2 | vivado | `100000000.0` | - | included |
 | `xilinx_ac701` | xilinx_ac701 | vivado | `100000000.0` | Ethernet, SPI Flash, PCIe | included |

litex_boards/platforms/trenz_tel0025.py

@@ -0,0 +1,158 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticeNexusPlatform
+from litex.build.openfpgaloader import OpenFPGALoader
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst
+    ("clk25",     0, Pins("C1"), IOStandard("LVCMOS33")), # CLK_25M.
+    ("clk25_aux", 0, Pins("G1"), IOStandard("LVCMOS33")), # CLK1_25M.
+    ("clk12",     0, Pins("E6"), IOStandard("LVCMOS33")), # CLK_12M.
+    ("user_btn_n", 0, Pins("C8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+
+    # Leds (RGB LED, active-low).
+    ("user_led", 0, Pins("A7"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("A8"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("B8"), IOStandard("LVCMOS33")),
+    ("rgb_led", 0,
+        Subsignal("r", Pins("A7")),
+        Subsignal("g", Pins("A8")),
+        Subsignal("b", Pins("B8")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    # Serial (FT2232H channel A).
+    ("serial", 0,
+        Subsignal("rx", Pins("D2"), IOStandard("LVCMOS33")), # ADBUS0 / FTDI TXD.
+        Subsignal("tx", Pins("B1"), IOStandard("LVCMOS33")), # ADBUS1 / FTDI RXD.
+    ),
+
+    # SPI Flash.
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("B4")),
+        Subsignal("clk",  Pins("B3")),
+        Subsignal("mosi", Pins("A4")),
+        Subsignal("miso", Pins("A5")),
+        Subsignal("wp",   Pins("A6")),
+        Subsignal("hold", Pins("B7")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=FAST"),
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("B4")),
+        Subsignal("clk",  Pins("B3")),
+        Subsignal("dq",   Pins("A4 A5 A6 B7")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=FAST"),
+    ),
+
+    # SDCard.
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("A10")),
+        Subsignal("mosi", Pins("A12"), Misc("PULLMODE=UP")),
+        Subsignal("cs_n", Pins("B12"), Misc("PULLMODE=UP")),
+        Subsignal("miso", Pins("B9"),  Misc("PULLMODE=UP")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=FAST"),
+    ),
+    ("sdcard", 0,
+        Subsignal("data", Pins("B9 A9 B13 B12"), Misc("PULLMODE=UP")),
+        Subsignal("cmd",  Pins("A12"),           Misc("PULLMODE=UP")),
+        Subsignal("clk",  Pins("A10")),
+        Subsignal("cd",   Pins("B14"),           Misc("PULLMODE=UP")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=FAST"),
+    ),
+
+    # HyperRAM.
+    ("hyperram", 0,
+        Subsignal("dq",    Pins("M4 K5 N4 K6 L7 P7 N7 M7"), IOStandard("LVCMOS18H")),
+        Subsignal("rwds",  Pins("N5"),                      IOStandard("LVCMOS18H")),
+        Subsignal("cs_n",  Pins("K4"),                      IOStandard("LVCMOS18H")),
+        Subsignal("rst_n", Pins("L4"),                      IOStandard("LVCMOS18H")),
+        Subsignal("clk_p", Pins("N6"),                      IOStandard("LVDS")),
+        Subsignal("clk_n", Pins("P6"),                      IOStandard("LVDS")),
+        Misc("SLEWRATE=FAST"),
+    ),
+
+    # CSI control GPIOs / I2C.
+    ("csi_i2c", 0,
+        Subsignal("sda", Pins("E2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl", Pins("E1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+    ("csi_i2c", 1,
+        Subsignal("scl", Pins("G5"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("sda", Pins("G6"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+    ("csi_gpio", 0,
+        Subsignal("gpio0", Pins("J6")),
+        Subsignal("gpio1", Pins("J5")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("csi_gpio", 1,
+        Subsignal("gpio0", Pins("H5")),
+        Subsignal("gpio1", Pins("H6")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    # CSI differential lanes, exposed for future video work.
+    # Use MIPI_DPHY on P lanes and LVCMOS12H on N lanes, as in Lattice examples.
+    ("csi", 0,
+        Subsignal("clk_p",  Pins("P11"),             IOStandard("MIPI_DPHY")),
+        Subsignal("clk_n",  Pins("N11"),             IOStandard("LVCMOS12H")),
+        Subsignal("data_p", Pins("N13 P12 P10 P8"),  IOStandard("MIPI_DPHY")),
+        Subsignal("data_n", Pins("N14 P13 N10 N8"),  IOStandard("LVCMOS12H")),
+    ),
+    ("csi", 1,
+        Subsignal("clk_p",  Pins("P9"),             IOStandard("MIPI_DPHY")),
+        Subsignal("clk_n",  Pins("N9"),             IOStandard("LVCMOS12H")),
+        Subsignal("data_p", Pins("M9 K9 M14 L13"),  IOStandard("MIPI_DPHY")),
+        Subsignal("data_n", Pins("L9 K10 M13 L14"), IOStandard("LVCMOS12H")),
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = [
+    # 2.54mm placeholder headers.
+    ("x", "C11 E10 E9 G10 F11 D11 D12 E11 B10 G13 G14 F13 F14 E13 E14 E12 D14 C14 G12 F10"),
+    ("y", "D13 C13 C10 C9"),
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticeNexusPlatform):
+    default_clk_name   = "clk25"
+    default_clk_period = 1e9/25e6
+
+    def __init__(self, toolchain="radiant", **kwargs):
+        LatticeNexusPlatform.__init__(
+            self,
+            "LFD2NX-40-7BG196I",
+            _io,
+            _connectors,
+            toolchain=toolchain,
+            **kwargs)
+
+        # SPI pins are reused by the LiteSPI core after configuration.
+        self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
+
+        # Evaluation mode with the free Radiant license.
+        if hasattr(self.toolchain, "set_prj_strategy_opts"):
+            self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
+
+    def create_programmer(self, cable="ft2232"):
+        return OpenFPGALoader(cable=cable)
+
+    def do_finalize(self, fragment):
+        LatticeNexusPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk25",     loose=True), 1e9/25e6)
+        self.add_period_constraint(self.lookup_request("clk25_aux", loose=True), 1e9/25e6)
+        self.add_period_constraint(self.lookup_request("clk12",     loose=True), 1e9/12e6)

litex_boards/targets/trenz_tel0025.py

@@ -0,0 +1,171 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.gen import *
+
+from litex_boards.platforms import trenz_tel0025
+
+from litex.soc.cores.clock import *
+from litex.soc.cores.hyperbus import HyperRAM
+from litex.soc.cores.led import LedChaser
+from litex.soc.integration.soc import *
+from litex.soc.integration.builder import *
+
+# Constants ----------------------------------------------------------------------------------------
+
+_HYPERRAM_SIZE  = 8*MEGABYTE
+_OPENSBI_OFFSET = 0x00f00000
+_OPENSBI_SIZE   = 0x00080000
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(LiteXModule):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
+        self.cd_sys = ClockDomain()
+        self.cd_por = ClockDomain()
+
+        # # #
+
+        # Clk / Rst
+        clk25      = platform.request("clk25")
+        user_btn_n = platform.request("user_btn_n")
+
+        # Built-in oscillator for power-on reset.
+        self.hf_clk = NXOSCA(platform)
+        self.hf_clk.create_hf_clk(self.cd_por, 25e6)
+
+        # Power-on reset.
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+        self.specials += AsyncResetSynchronizer(self.cd_por, ~user_btn_n)
+
+        # PLL.
+        self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
+        self.comb += sys_pll.reset.eq(self.rst | ~por_done)
+        sys_pll.register_clkin(clk25, 25e6)
+        sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~sys_pll.locked)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=50e6, toolchain="radiant",
+        with_hyperram       = True,
+        with_led_chaser     = True,
+        with_sdcard         = False,
+        with_spi_sdcard     = False,
+        with_spi_flash      = False,
+        **kwargs):
+        platform = trenz_tel0025.Platform(toolchain=toolchain)
+
+        # Linux -----------------------------------------------------------------------------------
+        # The SMP/Vexii Linux variants place OpenSBI at main_ram + 0x00f00000.
+        main_ram_size = kwargs.get("integrated_main_ram_size", 0) or 0
+        if with_hyperram and not main_ram_size:
+            main_ram_size = _HYPERRAM_SIZE
+        cpu_type    = kwargs.get("cpu_type", "vexriscv")
+        cpu_variant = kwargs.get("cpu_variant", None) or "standard"
+        with_opensbi = (
+            (cpu_type == "vexriscv_smp" and cpu_variant == "linux") or
+            (cpu_type == "vexiiriscv"   and cpu_variant in ["linux", "debian"])
+        )
+        if with_opensbi and main_ram_size < (_OPENSBI_OFFSET + _OPENSBI_SIZE):
+            raise ValueError(
+                "vexriscv_smp/vexiiriscv Linux variants place OpenSBI beyond "
+                "the TEL0025 8MiB HyperRAM window; use vexriscv linux instead."
+            )
+
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Trenz TEL0025", **kwargs)
+
+        # HyperRAM ---------------------------------------------------------------------------------
+        if with_hyperram and not self.integrated_main_ram_size:
+            self.hyperram = HyperRAM(
+                pads         = platform.request("hyperram"),
+                latency      = 7,
+                latency_mode = "variable",
+                sys_clk_freq = sys_clk_freq,
+                clk_ratio    = "4:1",
+            )
+            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(
+                origin = self.mem_map["main_ram"],
+                size   = _HYPERRAM_SIZE,
+                mode   = "rwx",
+            ))
+
+        # SPI Flash --------------------------------------------------------------------------------
+        if with_spi_flash:
+            from litespi.modules import MT25QL256A
+            from litespi.opcodes import SpiNorFlashOpCodes as Codes
+            self.add_spi_flash(
+                mode        = "4x",
+                module      = MT25QL256A(Codes.READ_1_1_4),
+                with_master = False,
+            )
+
+        # SDCard -----------------------------------------------------------------------------------
+        if with_sdcard:
+            self.add_sdcard()
+        if with_spi_sdcard:
+            self.add_spi_sdcard()
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq,
+                polarity     = 1,
+            )
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.build.parser import LiteXArgumentParser
+    parser = LiteXArgumentParser(platform=trenz_tel0025.Platform, description="LiteX SoC on Trenz TEL0025.")
+    parser.add_target_argument("--sys-clk-freq",   default=50e6,       type=float, help="System clock frequency.")
+    parser.add_target_argument("--no-hyperram",    action="store_true",            help="Disable HyperRAM support.")
+    parser.add_target_argument("--with-spi-flash", action="store_true",            help="Enable SPI Flash support.")
+    parser.add_target_argument("--flash",          action="store_true",            help="Flash bitstream to SPI Flash.")
+    sdopts = parser.target_group.add_mutually_exclusive_group()
+    sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
+    sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+        sys_clk_freq    = args.sys_clk_freq,
+        toolchain       = args.toolchain,
+        with_hyperram   = not args.no_hyperram,
+        with_sdcard     = args.with_sdcard,
+        with_spi_sdcard = args.with_spi_sdcard,
+        with_spi_flash  = args.with_spi_flash,
+        **parser.soc_argdict
+    )
+
+    builder = Builder(soc, **parser.builder_argdict)
+    if args.build:
+        builder.build(**parser.toolchain_argdict)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
+
+    if args.flash:
+        prog = soc.platform.create_programmer()
+        prog.flash(0, builder.get_bitstream_filename(mode="flash"), external=True)
+
+if __name__ == "__main__":
+    main()