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platforms/targets: Add MLK-CU07-KU15P support
Add the platform and reference LiteX target for the Milianke MLK-H5P-CU07-KU15P development board. Define the system and DDR reference clocks, UART, SD card, user LEDs and buttons, I2C, and the board's 4 GB 64-bit DDR4 interface. Add a target using the UltraScale+ DDR PHY, deterministic power-on reset, optional SD card support, and an optional LED chaser. Configure OpenFPGALoader and SPI x4 bitstream generation for the XCKU15P-FFVA1156-2-E device.
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‎docs/boards_inventory.md‎

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| `microphase_a7_lite` | microphase_a7_lite | vivado | `100000000.0` | Ethernet, SDCard, SPI SDCard, SPI Flash | included |
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| `microsoft_catapult_v3` | microsoft_catapult_v3 | quartus | `100000000.0` | - | included |
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| `mist` | mist | quartus | `50000000.0` | Video Terminal | included |
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| `mlk_cu07_ku15p` | mlk_cu07_ku15p | vivado | `75000000.0` | SDCard | included |
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| `mlkpai_fs01_dr1v90m` | mlkpai_fs01_dr1v90m | td | `25000000.0` | - | included |
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| `mnt_rkx7` | mnt_rkx7 | vivado | `100000000.0` | Ethernet, Etherbone, SDCard, SPI SDCard, SPI Flash, USB Host | included |
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| `muselab_icesugar` | muselab_icesugar | icestorm | `24000000.0` | - | included |

‎litex_boards/platforms/mlk_cu07_ku15p.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2026 Yu Jin <lambda.jinyu@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.openfpgaloader import OpenFPGALoader
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from litex.build.xilinx import XilinxUSPPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk100", 0, Pins("AH18"), IOStandard("LVCMOS18")),
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("clk100_ddr", 0,
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Subsignal("p", Pins("AK17")),
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Subsignal("n", Pins("AK16")),
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IOStandard("DIFF_SSTL12")
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),
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("cpu_resetn", 0, Pins("J23"), IOStandard("LVCMOS18"), Misc("PULLTYPE PULLUP")),
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# Buttons.
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("user_btn", 0, Pins("G26"), IOStandard("LVCMOS18")),
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("user_btn", 1, Pins("G25"), IOStandard("LVCMOS18")),
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("user_btn", 2, Pins("H24"), IOStandard("LVCMOS18")),
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# Leds.
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("user_led", 0, Pins("AP9"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AN9"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("AP8"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("AN8"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("AL10"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("AM10"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("AE11"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("AN13")),
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Subsignal("rx", Pins("AP13")),
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IOStandard("LVCMOS33")
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),
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# SDCard.
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("sdcard", 0,
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Subsignal("clk", Pins("B9")),
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Subsignal("cmd", Pins("A10"), Misc("PULLTYPE PULLUP")),
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Subsignal("data", Pins("B11 A9 C8 B10"), Misc("PULLTYPE PULLUP")),
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Subsignal("cd", Pins("C11"), Misc("PULLTYPE PULLUP")),
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IOStandard("LVCMOS18")
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),
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# Runtime QSPI is intentionally omitted. The source pin table assigns C8
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# to both SD D2 and flash CS, and the dedicated flash clock needs STARTUPE3.
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# I2C EEPROM / RTC.
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("i2c", 0,
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Subsignal("scl", Pins("AP11")),
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Subsignal("sda", Pins("AP10")),
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IOStandard("LVCMOS33")
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),
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# 4GB DDR4 SDRAM: 4 x Hynix H5AN8G6NCJR-VKI, modeled as MT40A512M16.
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("ddram", 0,
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Subsignal("a", Pins(
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"AM34 AN26 AP34 AK26 AL32 AK28 AK32 AL30",
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"AL34 AP26 AK31 AL33 AH32 AM32"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AJ31 AK27"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AJ30"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AJ33"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("AJ34"), IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("AJ28"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("AH33"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("AH31"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("Y26 V27 AA22 W23 AE25 AD21 AM21 AJ21"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AD25 AA27 AC24 AB25 AB24 AB27 AD26 AB26",
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"U25 W28 W26 W29 U24 V29 V26 Y28",
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"AB20 Y23 AC22 AA24 AA20 AA25 AC23 AA23",
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"U22 T22 T23 W21 U21 Y25 V21 W25",
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"AJ23 AF23 AJ24 AG25 AH23 AF24 AH22 AG24",
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"AG20 AE22 AF20 AF22 AD20 AE23 AG22 AE20",
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"AM22 AM24 AN22 AN24 AN23 AP24 AP23 AP25",
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"AL24 AL25 AK22 AL22 AK23 AM20 AL20 AL23"),
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IOStandard("POD12_DCI")),
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Subsignal("dqs_p", Pins("AC26 U26 AB21 V22 AH24 AG21 AP20 AJ20"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_n", Pins("AC27 U27 AC21 V23 AJ25 AH21 AP21 AK20"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("clk_p", Pins("AJ29"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("AK30"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AH27"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("AH28"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("AJ26"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xcku15p-ffva1156-2-e", _io, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader(fpga_part="xcku15p-ffva1156", cable="ft2232")
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def do_finalize(self, fragment):
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS true [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property CFGBVS GND [current_design]")
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self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN pulldown [current_design]")
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)

‎litex_boards/targets/mlk_cu07_ku15p.py‎

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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2026 Yu Jin <lambda.jinyu@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import mlk_cu07_ku15p
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from litex.soc.cores.clock import USMMCM, USIDELAYCTRL
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import SoCCore
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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clk100 = platform.request("clk100")
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platform.request("cpu_resetn")
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# Keep reset independent of the active-low button, which can float low
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# on some board revisions. The counter provides a deterministic POR.
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self.cd_por = ClockDomain()
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por_count = Signal(16, reset=2**16 - 1)
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por_done = Signal()
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self.comb += [
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self.cd_por.clk.eq(clk100),
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por_done.eq(por_count == 0),
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]
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq, with_reset=False)
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pll.create_clkout(self.cd_idelay, 400e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6), with_sdcard=False, with_led_chaser=False, **kwargs):
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platform = mlk_cu07_ku15p.Platform()
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self.crg = _CRG(platform, sys_clk_freq)
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SoCCore.__init__(
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self,
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platform,
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sys_clk_freq,
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ident="LiteX SoC on Milianke MLK-CU07-KU15P",
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**kwargs,
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)
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if not self.integrated_main_ram_size:
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self.ddrphy = usddrphy.USPDDRPHY(
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platform.request("ddram"),
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memtype="DDR4",
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sys_clk_freq=sys_clk_freq,
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iodelay_clk_freq=400e6,
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)
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self.add_sdram(
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"sdram",
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phy=self.ddrphy,
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module=MT40A512M16(sys_clk_freq, "1:4"),
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size=0x40000000,
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l2_cache_size=kwargs.get("l2_size", 8192),
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)
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if with_sdcard:
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self.add_sdcard()
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if with_led_chaser:
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self.leds = LedChaser(
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pads=platform.request_all("user_led"),
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sys_clk_freq=sys_clk_freq,
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(
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platform=mlk_cu07_ku15p.Platform,
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description="LiteX SoC on Milianke MLK-CU07-KU15P.",
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)
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parser.add_target_argument(
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"--sys-clk-freq",
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default=75e6,
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type=float,
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help="System clock frequency.",
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)
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parser.add_target_argument(
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"--with-sdcard",
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action="store_true",
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help="Enable SD card support.",
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)
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parser.add_target_argument(
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"--with-led-chaser",
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action="store_true",
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help="Enable LED chaser.",
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)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=args.sys_clk_freq,
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with_sdcard=args.with_sdcard,
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with_led_chaser=args.with_led_chaser,
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**parser.soc_argdict,
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()

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