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Add initial YPCB-00338-1P1 board support.
- Clk/Rst: OK. - Leds: OK. - PCIe Gen2 X8: OK. - Dual DDR3: 32-bit OK, need to extend to the full 64-bit + ECC in the future. DDR3: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2024 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on May 21 2025 09:55:09 BIOS CRC passed (8a7cd631) LiteX git sha1: 0d1484dd4 --=============== SoC ==================-- CPU: VexRiscv @ 125MHz BUS: wishbone 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 8.0KiB SDRAM: 1.0GiB 32-bit @ 1000MT/s (CL-8 CWL-6) MAIN-RAM: 512.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |00000000000000000000000000000000| delays: - m0, b01: |00000000000000000000000000000000| delays: - m0, b02: |00000000000000000000000000000000| delays: - m0, b03: |11111111000000000000000000000000| delays: 03+-03 m0, b04: |00000000001111111111000000000000| delays: 14+-04 m0, b05: |00000000000000000000000111111111| delays: 27+-04 m0, b06: |00000000000000000000000000000000| delays: - m0, b07: |00000000000000000000000000000000| delays: - best: m0, b04 delays: 14+-04 m1, b00: |00000000000000000000000000000000| delays: - m1, b01: |00000000000000000000000000000000| delays: - m1, b02: |00000000000000000000000000000000| delays: - m1, b03: |11111111100000000000000000000000| delays: 04+-04 m1, b04: |00000000000111111111100000000000| delays: 15+-04 m1, b05: |00000000000000000000000011111111| delays: 27+-03 m1, b06: |00000000000000000000000000000000| delays: - m1, b07: |00000000000000000000000000000000| delays: - best: m1, b04 delays: 15+-04 m2, b00: |00000000000000000000000000000000| delays: - m2, b01: |00000000000000000000000000000000| delays: - m2, b02: |00000000000000000000000000000000| delays: - m2, b03: |11111111000000000000000000000000| delays: 03+-03 m2, b04: |00000000011111111111000000000000| delays: 14+-05 m2, b05: |00000000000000000000000111111111| delays: 27+-04 m2, b06: |00000000000000000000000000000000| delays: - m2, b07: |00000000000000000000000000000000| delays: - best: m2, b04 delays: 14+-05 m3, b00: |00000000000000000000000000000000| delays: - m3, b01: |00000000000000000000000000000000| delays: - m3, b02: |00000000000000000000000000000000| delays: - m3, b03: |11111111100000000000000000000000| delays: 03+-03 m3, b04: |00000000001111111111000000000000| delays: 15+-05 m3, b05: |00000000000000000000000111111111| delays: 27+-03 m3, b06: |00000000000000000000000000000000| delays: - m3, b07: |00000000000000000000000000000000| delays: - best: m3, b04 delays: 14+-04 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 74.0MiB/s Read speed: 78.0MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> PCIe: 01:00.0 Memory controller: Xilinx Corporation Device 7028 Subsystem: Xilinx Corporation Device 0007 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: Memory at f7000000 (32-bit, non-prefetchable) [disabled] [size=1M] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [60] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 75.000W DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 256 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s, Exit Latency L0s unlimited ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s (ok), Width x8 (ok) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range B, TimeoutDis- NROPrPrP- LTR- 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix- EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- FRS- TPHComp- ExtTPHComp- AtomicOpsCap: 32bit- 64bit- 128bitCAS- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, AtomicOpsCtl: ReqEn- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1- EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest- Retimer- 2Retimers- CrosslinkRes: unsupported Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00
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‎litex_boards/platforms/ypcb_00338_1p1.py‎

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#!/usr/bin/env python3
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Florent Kermarrec <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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# The YPCB-00338-1P1 boards has been documented by @TiferKing:
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# - https://github.com/TiferKing/ypcb_00338_1p1_hack
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# - https://www.tiferking.cn/index.php/2024/12/19/650/
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# Features:
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# - XC7K480T-FFG1156-2.
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# - PCIe Gen2/3 x8.
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# - Dual 72-bit DDR3 (64 + 8 ECC).
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# - Linear BPI Flash (x16).
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# - LM73 temperature sensor + SMBus on edge connector.
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# - Three user LEDs.
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("AA28"), IOStandard("LVCMOS18")),
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("rst_n", 0, Pins("R28"), IOStandard("LVCMOS18")),
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# Leds.
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("user_led", 0, Pins("P30"), IOStandard("LVCMOS18")), # Red.
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("user_led", 1, Pins("M30"), IOStandard("LVCMOS18")), # Green.
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("user_led", 2, Pins("N30"), IOStandard("LVCMOS18")), # Yellow.
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# LM73 temperature sensor (I²C + ALERT).
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("lm73", 0,
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Subsignal("alert", Pins("P25")),
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Subsignal("scl", Pins("N24")),
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Subsignal("sda", Pins("N25")),
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IOStandard("LVCMOS18")
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),
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# PCIe (Gen2 X8).
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("pcie_i2c", 0,
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Subsignal("scl", Pins("R26")),
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Subsignal("sda", Pins("R27")),
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IOStandard("LVCMOS18")
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),
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("pcie_x1", 0,
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Subsignal("clk_p", Pins("J8")),
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Subsignal("clk_n", Pins("J7")),
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Subsignal("rst_n", Pins("Y26"), IOStandard("LVCMOS18")),
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Subsignal("tx_p", Pins("F2")),
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Subsignal("tx_n", Pins("F1")),
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Subsignal("rx_p", Pins("H6")),
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Subsignal("rx_n", Pins("H5")),
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),
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("pcie_x4", 0,
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Subsignal("clk_p", Pins("J8")),
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Subsignal("clk_n", Pins("J7")),
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Subsignal("rst_n", Pins("Y26"), IOStandard("LVCMOS18")),
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Subsignal("tx_p", Pins("F2 H2 K2 M2")),
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Subsignal("tx_n", Pins("F1 H1 K1 M1")),
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Subsignal("rx_p", Pins("H6 J4 K6 L4")),
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Subsignal("rx_n", Pins("H5 J3 K5 L3")),
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),
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("pcie_x8", 0,
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Subsignal("clk_p", Pins("J8")),
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Subsignal("clk_n", Pins("J7")),
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Subsignal("rst_n", Pins("Y26"), IOStandard("LVCMOS18")),
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Subsignal("tx_p", Pins("F2 H2 K2 M2 N4 P2 T2 U4")),
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Subsignal("tx_n", Pins("F1 H1 K1 M1 N3 P1 T1 U3")),
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Subsignal("rx_p", Pins("H6 J4 K6 L4 M6 P6 R4 T6")),
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Subsignal("rx_n", Pins("H5 J3 K5 L3 M5 P5 E3 T5")),
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),
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# Linear Flash (BPI x16).
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("linear_flash", 0,
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Subsignal("adr", Pins(
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# A[1] … A[25] (little-endian order).
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"AD26 AC25 AC29 AC28 AD27 AC27 AB25 AB28 AB27 AB26",
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"AA26 AA31 AA30 AB33 AB32 Y32 P32 R32 U33 T31",
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"T30 U31 U30 N34 P34"
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)),
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Subsignal("dq", Pins(
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# DQ[0] … DQ[15].
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"AA33 AA34 Y33 Y34 V32 V33 W31 W32 W30 V25",
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"W25 V29 W29 V28 W24 Y24"
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)),
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Subsignal("wen", Pins("T34")),
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Subsignal("oen", Pins("T33")),
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Subsignal("ce_n", Pins("V30")),
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Subsignal("adv", Pins("M31")),
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IOStandard("LVCMOS18"),
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Misc("SLEW=FAST"),
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),
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# DDR3 SDRAM – Channel 0.
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("ddram", 0,
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# Address / bank / control.
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Subsignal("a", Pins(
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"AK27 AN23 AL24 AK26 AH24 AH25 AL26 AJ24",
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"AJ25 AM23 AL28 AL25 AM25 AK24 AM27"
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), IOStandard("SSTL15")),
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Subsignal("ba", Pins("AM26 AP24 AN28"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AJ29"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AP26"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AN27"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AK28"), IOStandard("SSTL15")),
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Subsignal("cke", Pins("AP27"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AK29"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AD31"), IOStandard("SSTL15")),
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# Data / strobe / clock.
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Subsignal("dq", Pins(
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"AG17 AG16 AH17 AJ19 AH18 AH19 AJ16 AJ17",
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"AL20 AN17 AL19 AM16 AL18 AL16 AM20 AN18",
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"AL23 AN20 AK23 AP19 AN22 AN19 AM22 AP20",
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"AJ21 AH22 AK21 AG21 AG22 AG20 AH23 AG23",
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"AJ32 AK32 AK31 AL30 AL34 AL31 AK34 AL29",
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"AJ34 AH32 AJ30 AH34 AF31 AG30 AG31 AF30",
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"AE32 AC33 AF33 AC32 AD34 AC34 AE33 AE31",
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"AE26 AF29 AE24 AF28 AF24 AG25 AF26 AF25",
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"AN34 AP30 AM33 AN29 AP32 AP29 AM31 AP31" # ECC
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), IOStandard("SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins(
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"AK16 AM17 AP21 AH20 AK33 AG33 AE34 AE27 AN32"
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), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins(
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"AK17 AM18 AP22 AJ20 AL33 AH33 AF34 AE28 AP33"
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), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("AN25"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AP25"), IOStandard("DIFF_SSTL15")),
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Misc("SLEW=FAST"),
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),
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# DDR3 SDRAM – Channel 1.
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("ddram", 1,
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# Address / bank / control.
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Subsignal("a", Pins(
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"E27 C27 B28 D27 C24 D24 C25 A24",
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"A25 J24 F26 D26 H25 D25 B26"
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), IOStandard("SSTL15")),
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Subsignal("ba", Pins("F24 J25 E24"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("E28"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("E26"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("F25"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("F28"), IOStandard("SSTL15")),
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Subsignal("cke", Pins("A28"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("B27"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("F18"), IOStandard("SSTL15")),
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# Data / strobe / clock.
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Subsignal("dq", Pins(
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"A29 B33 A31 C33 C32 A30 B30 A33",
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"D31 F33 D30 D29 E33 E34 E31 F34",
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"B23 A21 C23 B20 B22 A23 C20 B21",
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"G31 G32 F29 F31 E29 G33 H33 H32",
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"B18 C17 C19 B16 A18 A16 C18 B17",
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"K27 L24 K24 L28 K26 M27 L25 M26",
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"F16 E18 E16 H19 H17 H20 E17 H18",
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"D20 F21 E23 G21 G20 D21 F20 F23",
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"L34 K34 K31 K33 L31 J30 L33 J34" # ECC
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), IOStandard("SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins(
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"B31 D34 A19 H29 D16 K28 G17 G22 K32"
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), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins(
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"B32 C34 A20 H30 D17 K29 G18 G23 J32"
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), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("B25"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("A26"), IOStandard("DIFF_SSTL15")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado"):
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device = "xc7k480t-ffg1156-2"
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 11]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 12]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 13]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 14]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 15]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 16]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 17]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 18]")
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def create_programmer(self):
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return OpenFPGALoader(fpga_part="xc7k480t", cable="digilent_hs2", freq=20e6)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)

‎litex_boards/targets/ypcb_00338_1p1.py‎

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#!/usr/bin/env python3
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Florent Kermarrec <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Build/Use:
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# ./ypcb_00338_1p1_target.py --uart-name=jtag_uart --with-pcie --build --load
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# litex_term jtag --jtag-config=openocd_xc7_ft232.cfg
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import os
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import ypcb_00338_1p1
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J256M16
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from litedram.phy import s7ddrphy
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from litedram.common import PHYPadsReducer
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG -------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk50 = platform.request("clk50")
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rst_n = platform.request("rst_n")
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# PLL.
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self.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=135)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# IDelayCtrl.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=125e6,
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dram_channel = 0,
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with_led_chaser = True,
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with_pcie = False,
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**kwargs):
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# Platform ---------------------------------------------------------------------------------
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platform = ypcb_00338_1p1.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore -------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on YPCB-00338-1P1", **kwargs)
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# DDR3 SDRAM ------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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assert dram_channel in (0, 1), "dram_channel must be 0 or 1"
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self.ddrphy = s7ddrphy.A7DDRPHY( # FIXME: DDR3 on HR Bank so no ODELAY, use A7DDRPHY as workaround for now.
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pads = PHYPadsReducer(platform.request("ddram", dram_channel), [0, 1, 2, 3]), # FIXME: Get all modules working.
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J256M16(sys_clk_freq, "1:4"),
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size = 0x20000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x8"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y23 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y22 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y21 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y20 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y19 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[4].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[5].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y17 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[6].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y16 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[7].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(platform.request_all("user_led"), sys_clk_freq)
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# Build ------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=ypcb_00338_1p1.Platform, description="LiteX SoC on YPCB-00338-1P1.")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_pcie = args.with_pcie,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()

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