Merge pull request #768 from litex-hub/efinix-target-cleanup

enjoy-digital · web-flow · commit 78eb0cf4af31 · 2026-07-27T18:47:32.000+02:00
targets/efinix: clean up defaults and board integrations
diff --git a/litex_boards/platforms/adiuvo_forgix.py b/litex_boards/platforms/adiuvo_forgix.py
@@ -90,4 +90,6 @@ def __init__(self, toolchain="efinity"):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_t120_f576_dev_kit.py b/litex_boards/platforms/efinix_t120_f576_dev_kit.py
@@ -170,6 +170,15 @@ def usb_pmod_io(pmod):
         ),
     ]
 
+def i2c_pmod_io(pmod):
+    return [
+        ("i2c", 0,
+            Subsignal("sda", Pins(f"{pmod}:0")),
+            Subsignal("scl", Pins(f"{pmod}:1")),
+            IOStandard("3.3_V_LVTTL_/_LVCMOS"),
+        ),
+    ]
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(EfinixPlatform):
@@ -185,4 +194,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk40", loose=True), 1e9/40e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_t20_f256_dev_kit.py b/litex_boards/platforms/efinix_t20_f256_dev_kit.py
@@ -124,4 +124,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_t20_mipi_dev_kit.py b/litex_boards/platforms/efinix_t20_mipi_dev_kit.py
@@ -108,4 +108,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_t8_f81_dev_kit.py b/litex_boards/platforms/efinix_t8_f81_dev_kit.py
@@ -50,8 +50,8 @@
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(EfinixPlatform):
-    default_clk_name = "clk33"
-    default_clk_freq = 33.333e6
+    default_clk_name   = "clk33"
+    default_clk_freq   = 33.333e6
     default_clk_period = 1e9/33.333e6
 
     def __init__(self, toolchain="efinity"):
@@ -62,4 +62,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.333e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_ti375_c529_dev_kit.py b/litex_boards/platforms/efinix_ti375_c529_dev_kit.py
@@ -312,4 +312,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_ti60_f225_dev_kit.py b/litex_boards/platforms/efinix_ti60_f225_dev_kit.py
@@ -194,4 +194,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_tz170_j484_dev_kit.py b/litex_boards/platforms/efinix_tz170_j484_dev_kit.py
@@ -206,6 +206,20 @@
     ),
 ]
 
+# DDR Configuration --------------------------------------------------------------------------------
+
+ddr_config = {
+    "memory_type"     : "LPDDR4",
+    "memory_density"  : "8G",
+    "clkin_sel"       : "CLKIN 2",
+    "location"        : "DDR_0",
+    "dq_width"        : 32,
+    "physical_rank"   : 1,
+    "data_width"      : 512,
+    "address_width"   : 33,
+    "id_width"        : 8,
+}
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(EfinixPlatform):
@@ -215,10 +229,14 @@ class Platform(EfinixPlatform):
 
     def __init__(self, toolchain="efinity"):
         EfinixPlatform.__init__(self, "Tz170J484I3", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain, spi_width="4")
+        self.ddr_config = ddr_config
+        self.ddr_size   = 0x4000_0000 # 1GB.
 
     def create_programmer(self):
         return EfinixProgrammer(family=self.family)
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/efinix_xyloni_dev_kit.py b/litex_boards/platforms/efinix_xyloni_dev_kit.py
@@ -70,8 +70,8 @@
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(EfinixPlatform):
-    default_clk_name = "clk33"
-    default_clk_freq = 33.333e6
+    default_clk_name   = "clk33"
+    default_clk_freq   = 33.333e6
     default_clk_period = 1e9/33.333e6
 
     def __init__(self, toolchain="efinity"):
@@ -82,4 +82,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.333e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/platforms/jungle_electronics_fireant.py b/litex_boards/platforms/jungle_electronics_fireant.py
@@ -60,4 +60,6 @@ def create_programmer(self):
 
     def do_finalize(self, fragment):
         EfinixPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.33e6)
+        self.add_period_constraint(
+            self.lookup_request(self.default_clk_name, loose=True),
+            self.default_clk_period)
diff --git a/litex_boards/targets/efinix_t120_f576_dev_kit.py b/litex_boards/targets/efinix_t120_f576_dev_kit.py
@@ -7,15 +7,15 @@
 # Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
-import time
-
 from migen import *
 
 from litex.gen import *
 from litex.gen.genlib.misc import WaitTimer
 
 from litex_boards.platforms import efinix_t120_f576_dev_kit
 
+from litex.build.generic_platform import Pins, Subsignal, IOStandard
+
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import *
 from litex.soc.integration.soc import SoCRegion
@@ -40,13 +40,13 @@ def __init__(self, platform, sys_clk_freq):
 
         self.comb += self.cd_rst.clk.eq(clk40)
 
-         # A pulse is necessary to do a reset.
+        # A pulse is necessary to do a reset.
         self.rst_pulse = Signal()
         self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq))
         self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
         self.comb += reset_timer.wait.eq(self.rst)
 
-        # PLL
+        # PLL.
         self.pll = pll = TRIONPLL(platform)
         self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
         pll.register_clkin(clk40, platform.default_clk_freq)
@@ -65,13 +65,14 @@ def __init__(self, sys_clk_freq=75e6,
         remote_ip       = None,
         eth_dynamic_ip  = False,
         with_led_chaser = True,
+        with_i2c        = False,
         **kwargs):
         platform = efinix_t120_f576_dev_kit.Platform()
 
-        # USBUART PMOD as Serial--------------------------------------------------------------------
+        # USB-UART PMOD as Serial ------------------------------------------------------------------
         platform.add_extension(efinix_t120_f576_dev_kit.usb_pmod_io("pmod_e"))
         if kwargs.get("uart_name", "serial") == "serial":
-            if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "usb_uart"
+            kwargs["uart_name"] = "usb_uart"
 
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
@@ -91,15 +92,11 @@ def __init__(self, sys_clk_freq=75e6,
                 pads         = platform.request_all("user_led"),
                 sys_clk_freq = sys_clk_freq)
 
-        # Tristate Test ----------------------------------------------------------------------------
-        from litex.build.generic_platform import Subsignal, Pins, IOStandard
-        from litex.soc.cores.bitbang import I2CMaster
-        platform.add_extension([("i2c", 0,
-            Subsignal("sda",   Pins("T12")),
-            Subsignal("scl",   Pins("V11")),
-            IOStandard("3.3_V_LVTTL_/_LVCMOS"),
-        )])
-        self.i2c = I2CMaster(pads=platform.request("i2c"))
+        # I2C ---------------------------------------------------------------------------------------
+        if with_i2c:
+            from litex.soc.cores.bitbang import I2CMaster
+            platform.add_extension(efinix_t120_f576_dev_kit.i2c_pmod_io("pmod_a"))
+            self.i2c = I2CMaster(pads=platform.request("i2c"))
 
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet or with_etherbone:
@@ -111,15 +108,13 @@ def __init__(self, sys_clk_freq=75e6,
                 msg += "- rx_ctl: a wire must be soldered between R120 and R174\n"
                 msg += "- tx_ctl: a wire must be soldered between ETH1_TXEN (Pad 30) and R173\n"
                 print(msg)
-                time.sleep(2)
                 self.ethphy = LiteEthPHYRGMII(
                     platform           = platform,
                     clock_pads         = platform.request("eth_clocks", eth_phy),
                     pads               = platform.request("eth", eth_phy),
                     with_hw_init_reset = False)
             # Use Ethernet RMII PMOD.
             else:
-                from litex.build.generic_platform import Pins, Subsignal, IOStandard
                 def eth_lan8720_rmii_pmod_io(pmod):
                     # Lan8020 RMII PHY "PMOD": To be used as a PMOD, MDIO should be disconnected and TX1 connected to PMOD8 IO.
                     return [
@@ -392,19 +387,21 @@ def main():
     parser.add_target_argument("--flash",          action="store_true",      help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",   default=75e6, type=float, help="System clock frequency.")
     parser.add_target_argument("--with-spi-flash", action="store_true",      help="Enable memory-mapped SPI flash.")
+    parser.add_target_argument("--with-i2c",       action="store_true",      help="Enable I2C on PMOD A.")
     ethopts = parser.target_group.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support.")
     ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
     parser.add_target_argument("--eth-ip",         default="192.168.1.50",  help="Ethernet/Etherbone IP address.")
     parser.add_target_argument("--eth-dynamic-ip", action="store_true",     help="Enable dynamic Ethernet IP assignment.")
     parser.add_target_argument("--remote-ip",      default="192.168.1.100", help="Remote IP address of TFTP server.")
     parser.add_target_argument("--eth-rgmii-phy",  action="store_true",     help="Uses onboard RGMII Phy instead of RMII PMOD.")
-    parser.add_target_argument("--eth-phy",        default=0, type=int,     help="Ethernet PHY: 0 (default) or 1. (Only available with --eth-rgmii-phy")
+    parser.add_target_argument("--eth-phy",        default=0, type=int, choices=[0, 1], help="Ethernet PHY (only available with --eth-rgmii-phy).")
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq   = args.sys_clk_freq,
         with_spi_flash = args.with_spi_flash,
+        with_i2c       = args.with_i2c,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         eth_ip         = args.eth_ip,
diff --git a/litex_boards/targets/efinix_t20_f256_dev_kit.py b/litex_boards/targets/efinix_t20_f256_dev_kit.py
@@ -60,7 +60,7 @@ def __init__(self, platform, sys_clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=45e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
         platform = efinix_t20_f256_dev_kit.Platform()
 
         # CRG --------------------------------------------------------------------------------------
@@ -70,7 +70,7 @@ def __init__(self, sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=Tru
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", **kwargs)
 
         # SDR SDRAM --------------------------------------------------------------------------------
-        if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
+        if not self.integrated_main_ram_size and sys_clk_freq <= 50e6:
             self.specials += ClkOutput(ClockSignal("sys_ps"), platform.request("sdram_clock"))
 
             self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
@@ -106,7 +106,7 @@ def main():
     soc = BaseSoC(
         sys_clk_freq   = args.sys_clk_freq,
         with_spi_flash = args.with_spi_flash,
-         **parser.soc_argdict)
+        **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
     if args.build:
         builder.build(**parser.toolchain_argdict)
@@ -117,7 +117,7 @@ def main():
 
     if args.flash:
         from litex.build.openfpgaloader import OpenFPGALoader
-        prog = OpenFPGALoader("trion_t120_bga576")
+        prog = OpenFPGALoader("trion_t20_bga256")
         prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
 
 if __name__ == "__main__":
diff --git a/litex_boards/targets/efinix_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_t20_mipi_dev_kit.py
@@ -35,13 +35,13 @@ def __init__(self, platform, sys_clk_freq):
 
         self.comb += self.cd_rst.clk.eq(clk50)
 
-         # A pulse is necessary to do a reset.
+        # A pulse is necessary to do a reset.
         self.rst_pulse = Signal()
         self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq))
         self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
         self.comb += reset_timer.wait.eq(self.rst)
 
-        # PLL
+        # PLL.
         self.pll = pll = TRIONPLL(platform)
         self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
         pll.register_clkin(clk50, platform.default_clk_freq)
@@ -81,10 +81,10 @@ def main():
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable memory-mapped SPI flash.")
     args = parser.parse_args()
 
-    soc     = BaseSoC(
+    soc = BaseSoC(
         sys_clk_freq   = args.sys_clk_freq,
         with_spi_flash = args.with_spi_flash,
-         **parser.soc_argdict)
+        **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
     if args.build:
         builder.build(**parser.toolchain_argdict)
@@ -95,7 +95,7 @@ def main():
 
     if args.flash:
         from litex.build.openfpgaloader import OpenFPGALoader
-        prog = OpenFPGALoader("trion_t120_bga576")
+        prog = OpenFPGALoader("trion_t20_bga256")
         prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
 
 if __name__ == "__main__":
diff --git a/litex_boards/targets/efinix_t8_f81_dev_kit.py b/litex_boards/targets/efinix_t8_f81_dev_kit.py
@@ -61,6 +61,9 @@ def __init__(self, bios_flash_offset, sys_clk_freq=33.333e6, with_led_chaser=Tru
         # SoCCore ----------------------------------------------------------------------------------
         # Disable Integrated ROM.
         kwargs["integrated_rom_size"]  = 0
+        # Use Crossover UART by default.
+        if kwargs.get("uart_name", "serial") == "serial":
+            kwargs["uart_name"] = "crossover"
         # Set CPU variant / reset address
         if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
             kwargs["cpu_variant"] = "minimal"
diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py
@@ -88,21 +88,21 @@ class BaseSoC(SoCCore):
     }}
 
     def __init__(self,
-            sys_clk_freq   = 100e6,
-            cpu_clk_freq   = 100e6,
-            with_spi_flash = False,
+            sys_clk_freq     = 100e6,
+            cpu_clk_freq     = 100e6,
+            with_spi_flash   = False,
             spi_flash_number = 0,
-            spi_flash_rate = "1:1",
-            with_ethernet  = False,
-            with_etherbone = False,
-            with_ptp       = False,
-            eth_phy        = "rgmii",
-            eth_ip         = "192.168.1.50",
-            remote_ip      = None,
-            eth_dynamic_ip = False,
-            ptp_p2p        = False,
-            ptp_debug      = False,
-            with_ohci      = False,
+            spi_flash_rate   = "1:2",
+            with_ethernet    = False,
+            with_etherbone   = False,
+            with_ptp         = False,
+            eth_phy          = "rgmii",
+            eth_ip           = "192.168.1.50",
+            remote_ip        = None,
+            eth_dynamic_ip   = False,
+            ptp_p2p          = False,
+            ptp_debug        = False,
+            with_ohci        = False,
             **kwargs):
         platform = efinix_ti375_c529_dev_kit.Platform()
 
@@ -403,7 +403,7 @@ def __init__(self,
             # (integer) of the reference clock. If all your system clocks do not fall within
             # this range, you should dedicate one unused clock for CLKOUT0.
             pll3.create_clkout(None, 125e6, with_reset=True)
-            pll3.create_clkout(self.cd_eth_rx, 125e6,phase =270)
+            pll3.create_clkout(self.cd_eth_rx, 125e6, phase=270)
 
             platform.add_false_path_constraints(self.crg.cd_sys.clk, self.cd_eth.clk)
 
@@ -456,7 +456,7 @@ def main():
     parser = LiteXArgumentParser(platform=efinix_ti375_c529_dev_kit.Platform, description="LiteX SoC on Efinix Ti375 C529 Dev Kit.")
     parser.add_target_argument("--flash",            action="store_true",                             help="Flash bitstream.")
     parser.add_target_argument("--sys-clk-freq",     default=100e6, type=float,                       help="System clock frequency.")
-    parser.add_target_argument("--cpu-clk-freq",     default=100e6, type=float,                       help="System clock frequency.")
+    parser.add_target_argument("--cpu-clk-freq",     default=100e6, type=float,                       help="CPU clock frequency.")
     parser.add_target_argument("--with-spi-flash",   action="store_true",                             help="Enable SPI Flash.")
     parser.add_target_argument("--spi-flash-number", default=0, type=int, choices=[0, 1],             help="SPI Flash number.")
     parser.add_target_argument("--spi-flash-rate",   default="1:2", type=str, choices=["1:1", "1:2"], help="SPI Flash rate.")
diff --git a/litex_boards/targets/efinix_tz170_j484_dev_kit.py b/litex_boards/targets/efinix_tz170_j484_dev_kit.py
diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py
diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py
