targets: limit Mercury KX2 SDRAM window

Cap the LiteX-visible SDRAM region to 1 GiB so the corrected H5TC4G63CFR geometry does not overlap VexRiscv's default IO window at 0x80000000.

The DRAM controller still uses the real module geometry; this only limits the bus aperture exported as main_ram, matching the pattern used by other large-memory targets.

Author: enjoy-digital

litex_boards/targets/enclustra_mercury_kx2.py

@@ -66,6 +66,7 @@ def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, with_st1_baseboard=
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
                 module        = H5TC4G63CFR(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
                 l2_cache_size = kwargs.get("l2_size", 8192)
             )