targets: Reset Tang Mega 138K sys domain for DDR3

The Tang Mega 138K GW5 DDR3 CRG disables the PLL-generated reset on cd_sys when DDR3 is enabled, but then attached the explicit reset synchronizer to cd_sys2x. That left the sys-domain controller and software-visible logic without the reset used by the other GW5 DDR3 targets.

Attach the explicit DDR3 reset synchronizer to cd_sys, matching the Tang Console and Tang Mega 138K Pro CRGs. The gated sys2x clock remains generated through DHCE as before.

Author: enjoy-digital

litex_boards/targets/sipeed_tang_mega_138k.py

@@ -106,7 +106,7 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0,
                     i_CEN    = self.stop,
                     o_CLKOUT = self.cd_sys2x.clk
                 ),
-                AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
+                AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
             ]
             # Init clock domain
             self.comb += [