terasic_atum_a3_nano: Add Agilex 3 HPS (agilex_hps) CPU support.

Allow building with --cpu-type=agilex_hps (Agilex 3 HPS as the SoC's CPU, CSRs
via the LW bridge). The board has no LPDDR4/HPS-EMIF pins wired yet, so the
fabric SDR SDRAM is skipped and v1 exposes CSR access only; add cpu.add_emif()
once the board's HPS DRAM configuration is known.

Author: enjoy-digital

litex_boards/targets/terasic_atum_a3_nano.py

@@ -99,6 +99,12 @@ def __init__(self, sys_clk_freq=50e6,
 
         with_hdmi = with_video_colorbars or with_video_terminal or with_video_framebuffer
         with_eth  = with_ethernet or with_etherbone
+        with_hps  = (kwargs.get("cpu_type", None) == "agilex_hps")
+        if with_hps:
+            # The Agilex 3 HPS is the SoC's CPU: console on HPS UART0, no fabric SRAM.
+            kwargs["cpu_variant"]          = kwargs.get("cpu_variant") or "agilex3"
+            kwargs["with_uart"]            = False
+            kwargs["integrated_sram_size"] = 0
 
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate, with_hdmi=with_hdmi, with_eth=with_eth)
@@ -135,7 +141,10 @@ def __init__(self, sys_clk_freq=50e6,
                 self.add_video_framebuffer(phy=self.videophy, timings="800x600@75Hz", clock_domain="init")
 
         # SDR SDRAM --------------------------------------------------------------------------------
-        if not self.integrated_main_ram_size:
+        # Note: with the Agilex 3 HPS, the fabric SDR SDRAM is skipped; the HPS DDR (LPDDR4 via an
+        # HPS-EMIF) is not wired on this board yet, so v1 exposes CSR access through the LW bridge
+        # only. Add cpu.add_emif(...) here once the board's HPS DRAM pins/config are known.
+        if not with_hps and not self.integrated_main_ram_size:
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",