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targets: uses self.cpu.set_libxil instead of explicit/dupplicated code for all boards based on zynq7000/zynmpMP
1 parent 2f06d08 commit 8c3c46b

8 files changed

Lines changed: 54 additions & 397 deletions

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‎litex_boards/targets/alinx_axu2cga.py‎

Lines changed: 9 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -16,17 +16,12 @@
1616
# Relies on https://github.com/lucaceresoli/zynqmp-pmufw-builder to create a generic PMU firmware;
1717
# first build will take a while because it includes a cross-toolchain.
1818

19-
import os
20-
2119
from migen import *
2220

2321
from litex.gen import *
2422

2523
from litex_boards.platforms import alinx_axu2cga
2624

27-
from litex.build.tools import write_to_file
28-
29-
3025
from litex.soc.cores.clock import *
3126
from litex.soc.integration.soc import *
3227
from litex.soc.integration.soc import SoCRegion
@@ -89,70 +84,22 @@ def __init__(self, sys_clk_freq=25e6, with_led_chaser=True, **kwargs):
8984
linker = True)
9085
)
9186
self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127
87+
self.cpu.set_libxil({
88+
"STDIN_BASEADDRESS" : "0xFF010000",
89+
"STDOUT_BASEADDRESS" : "0xFF010000",
90+
"XPAR_PSU_DDR_0_S_AXI_BASEADDR" : "0x00000000",
91+
"XPAR_PSU_DDR_0_S_AXI_HIGHADDR" : "0x7FFFFFFF",
92+
"XPAR_PSU_DDR_1_S_AXI_BASEADDR" : "0x800000000",
93+
"XPAR_PSU_DDR_1_S_AXI_HIGHADDR" : "0x87FFFFFFF",
94+
"XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ" : "99999005",
95+
})
9296

9397
# Leds -------------------------------------------------------------------------------------
9498
if with_led_chaser:
9599
self.leds = LedChaser(
96100
pads = platform.request_all("user_led"),
97101
sys_clk_freq = sys_clk_freq)
98102

99-
def finalize(self, *args, **kwargs):
100-
super(BaseSoC, self).finalize(*args, **kwargs)
101-
if self.cpu_type != "zynqmp":
102-
return
103-
104-
libxil_path = os.path.join(self.builder.software_dir, 'libxil')
105-
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
106-
lib = os.path.join(libxil_path, 'embeddedsw')
107-
if not os.path.exists(lib):
108-
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
109-
110-
os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
111-
112-
for header in [
113-
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
114-
'lib/bsp/standalone/src/common/xil_types.h',
115-
'lib/bsp/standalone/src/common/xil_assert.h',
116-
'lib/bsp/standalone/src/common/xil_io.h',
117-
'lib/bsp/standalone/src/common/xil_printf.h',
118-
'lib/bsp/standalone/src/common/xstatus.h',
119-
'lib/bsp/standalone/src/common/xdebug.h',
120-
'lib/bsp/standalone/src/arm/ARMv8/64bit/xpseudo_asm.h',
121-
'lib/bsp/standalone/src/arm/ARMv8/64bit/xreg_cortexa53.h',
122-
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h',
123-
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_errata.h',
124-
'lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h',
125-
'lib/bsp/standalone/src/arm/common/xil_exception.h',
126-
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
127-
]:
128-
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
129-
130-
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'), """
131-
#ifndef BSPCONFIG_H
132-
#define BSPCONFIG_H
133-
134-
#define EL3 1
135-
#define EL1_NONSECURE 0
136-
137-
#endif
138-
""")
139-
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
140-
#ifndef XPARAMETERS_H
141-
#define XPARAMETERS_H
142-
143-
#include "xparameters_ps.h"
144-
145-
#define STDIN_BASEADDRESS 0xFF010000
146-
#define STDOUT_BASEADDRESS 0xFF010000
147-
#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
148-
#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
149-
#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
150-
#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
151-
#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99999005
152-
153-
#endif
154-
''')
155-
156103
# Build --------------------------------------------------------------------------------------------
157104

158105
def main():
@@ -168,10 +115,6 @@ def main():
168115
**parser.soc_argdict
169116
)
170117
builder = Builder(soc, **parser.builder_argdict)
171-
if args.cpu_type == "zynqmp":
172-
soc.builder = builder
173-
builder.add_software_package('libxil')
174-
builder.add_software_library('libxil')
175118
if args.build:
176119
builder.build(**parser.toolchain_argdict)
177120

‎litex_boards/targets/digilent_arty_z7.py‎

Lines changed: 5 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,6 @@
3232
from litex.gen import *
3333

3434
from litex_boards.platforms import digilent_arty_z7
35-
from litex.build.tools import write_to_file
36-
3735

3836
from litex.soc.cores.clock import *
3937
from litex.soc.integration.soc import *
@@ -107,58 +105,18 @@ def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=125e6,
107105
)
108106
self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
109107
self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx"))
108+
self.cpu.set_libxil({
109+
"STDOUT_BASEADDRESS" : "0xE0000000",
110+
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
111+
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
112+
})
110113

111114
# Leds -------------------------------------------------------------------------------------
112115
if with_led_chaser:
113116
self.leds = LedChaser(
114117
pads = platform.request_all("user_led"),
115118
sys_clk_freq = sys_clk_freq)
116119

117-
def finalize(self, *args, **kwargs):
118-
super(BaseSoC, self).finalize(*args, **kwargs)
119-
if self.cpu_type != "zynq7000":
120-
return
121-
122-
libxil_path = os.path.join(self.builder.software_dir, 'libxil')
123-
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
124-
lib = os.path.join(libxil_path, 'embeddedsw')
125-
if not os.path.exists(lib):
126-
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
127-
128-
os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
129-
for header in [
130-
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
131-
'lib/bsp/standalone/src/common/xil_types.h',
132-
'lib/bsp/standalone/src/common/xil_assert.h',
133-
'lib/bsp/standalone/src/common/xil_io.h',
134-
'lib/bsp/standalone/src/common/xil_printf.h',
135-
'lib/bsp/standalone/src/common/xstatus.h',
136-
'lib/bsp/standalone/src/common/xdebug.h',
137-
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
138-
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
139-
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
140-
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
141-
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
142-
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
143-
'lib/bsp/standalone/src/arm/common/xil_exception.h',
144-
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
145-
]:
146-
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
147-
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
148-
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
149-
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
150-
#ifndef __XPARAMETERS_H
151-
#define __XPARAMETERS_H
152-
153-
#include "xparameters_ps.h"
154-
155-
#define STDOUT_BASEADDRESS 0xE0000000
156-
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
157-
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
158-
159-
#endif
160-
''')
161-
162120
# Build --------------------------------------------------------------------------------------------
163121

164122
def main():
@@ -177,10 +135,6 @@ def main():
177135
**parser.soc_argdict
178136
)
179137
builder = Builder(soc, **parser.builder_argdict)
180-
if args.cpu_type == "zynq7000":
181-
soc.builder = builder
182-
builder.add_software_package('libxil')
183-
builder.add_software_library('libxil')
184138
if args.build:
185139
builder.build(**parser.toolchain_argdict)
186140

‎litex_boards/targets/digilent_zedboard.py‎

Lines changed: 6 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,6 @@
1111
from litex.gen import *
1212

1313
from litex_boards.platforms import digilent_zedboard
14-
from litex.build.tools import write_to_file
15-
1614

1715
from litex.soc.cores.clock import *
1816
from litex.soc.integration.soc import *
@@ -57,7 +55,7 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_led_chaser=True,
5755
platform.add_extension(usb_pmod_io("pmodb"))
5856
if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "usb_uart"
5957
else:
60-
kwargs["no_uart"] = True
58+
kwargs["with_uart"] = False
6159

6260
# CRG --------------------------------------------------------------------------------------
6361
use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
@@ -84,58 +82,18 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_led_chaser=True,
8482
linker = True)
8583
)
8684
self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
85+
self.cpu.set_libxil({
86+
"STDOUT_BASEADDRESS" : "0xE0001000",
87+
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
88+
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x3FFFFFFF",
89+
})
8790

8891
# Leds -------------------------------------------------------------------------------------
8992
if with_led_chaser:
9093
self.leds = LedChaser(
9194
pads = platform.request_all("user_led"),
9295
sys_clk_freq = sys_clk_freq)
9396

94-
def finalize(self, *args, **kwargs):
95-
super(BaseSoC, self).finalize(*args, **kwargs)
96-
if self.cpu_type != "zynq7000":
97-
return
98-
99-
libxil_path = os.path.join(self.builder.software_dir, 'libxil')
100-
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
101-
lib = os.path.join(libxil_path, 'embeddedsw')
102-
if not os.path.exists(lib):
103-
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
104-
105-
os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
106-
for header in [
107-
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
108-
'lib/bsp/standalone/src/common/xil_types.h',
109-
'lib/bsp/standalone/src/common/xil_assert.h',
110-
'lib/bsp/standalone/src/common/xil_io.h',
111-
'lib/bsp/standalone/src/common/xil_printf.h',
112-
'lib/bsp/standalone/src/common/xstatus.h',
113-
'lib/bsp/standalone/src/common/xdebug.h',
114-
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
115-
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
116-
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
117-
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
118-
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
119-
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
120-
'lib/bsp/standalone/src/arm/common/xil_exception.h',
121-
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
122-
]:
123-
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
124-
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
125-
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
126-
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
127-
#ifndef __XPARAMETERS_H
128-
#define __XPARAMETERS_H
129-
130-
#include "xparameters_ps.h"
131-
132-
#define STDOUT_BASEADDRESS 0xE0001000
133-
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
134-
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
135-
136-
#endif
137-
''')
138-
13997
# Build --------------------------------------------------------------------------------------------
14098

14199
def main():
@@ -151,10 +109,6 @@ def main():
151109
**parser.soc_argdict
152110
)
153111
builder = Builder(soc, **parser.builder_argdict)
154-
if args.cpu_type == "zynq7000":
155-
soc.builder = builder
156-
builder.add_software_package('libxil')
157-
builder.add_software_library('libxil')
158112
if args.build:
159113
builder.build(**parser.toolchain_argdict)
160114

‎litex_boards/targets/puzhi_p7_starlite.py‎

Lines changed: 5 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,6 @@
1212

1313
from litex_boards.platforms import puzhi_p7_starlite
1414

15-
from litex.build.tools import write_to_file
16-
1715
from litex.soc.integration.soc import *
1816
from litex.soc.integration.soc import SoCRegion
1917
from litex.soc.integration.builder import *
@@ -119,6 +117,11 @@ def __init__(self, variant="xc7z020", toolchain="vivado", sys_clk_freq=100e6,
119117

120118
# Enable SDIO.
121119
self.cpu.add_sdio(0, "MIO 40 .. 45", None, None, None)
120+
self.cpu.set_libxil({
121+
"STDOUT_BASEADDRESS" : "0xE0000000",
122+
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
123+
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
124+
})
122125

123126
if not with_ps7 and (with_ethernet or with_etherbone):
124127
self.ethphy = LiteEthPHYRGMII(
@@ -135,51 +138,6 @@ def __init__(self, variant="xc7z020", toolchain="vivado", sys_clk_freq=100e6,
135138
pads = platform.request_all("user_led"),
136139
sys_clk_freq = sys_clk_freq)
137140

138-
def finalize(self, *args, **kwargs):
139-
super(BaseSoC, self).finalize(*args, **kwargs)
140-
if self.cpu_type != "zynq7000":
141-
return
142-
143-
libxil_path = os.path.join(self.builder.software_dir, 'libxil')
144-
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
145-
lib = os.path.join(libxil_path, 'embeddedsw')
146-
if not os.path.exists(lib):
147-
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
148-
149-
os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
150-
for header in [
151-
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
152-
'lib/bsp/standalone/src/common/xil_types.h',
153-
'lib/bsp/standalone/src/common/xil_assert.h',
154-
'lib/bsp/standalone/src/common/xil_io.h',
155-
'lib/bsp/standalone/src/common/xil_printf.h',
156-
'lib/bsp/standalone/src/common/xstatus.h',
157-
'lib/bsp/standalone/src/common/xdebug.h',
158-
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
159-
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
160-
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
161-
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
162-
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
163-
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
164-
'lib/bsp/standalone/src/arm/common/xil_exception.h',
165-
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
166-
]:
167-
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
168-
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
169-
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
170-
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
171-
#ifndef __XPARAMETERS_H
172-
#define __XPARAMETERS_H
173-
174-
#include "xparameters_ps.h"
175-
176-
#define STDOUT_BASEADDRESS 0xE0000000
177-
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
178-
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
179-
180-
#endif
181-
''')
182-
183141
# Build --------------------------------------------------------------------------------------------
184142

185143
def main():
@@ -213,11 +171,6 @@ def main():
213171
)
214172

215173
builder = Builder(soc, **parser.builder_argdict)
216-
if args.cpu_type == "zynq7000":
217-
soc.builder = builder
218-
builder.add_software_package('libxil')
219-
builder.add_software_library('libxil')
220-
221174
if args.build:
222175
builder.build(**parser.toolchain_argdict)
223176

‎litex_boards/targets/redpitaya.py‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,12 @@ def __init__(self, board, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
9191
# Enable Ethernet.
9292
self.cpu.add_ethernet(0, "MIO 16 .. 27", "MIO 52 .. 53")
9393

94+
self.cpu.set_libxil({
95+
"STDOUT_BASEADDRESS" : "XPS_UART0_BASEADDR",
96+
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
97+
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
98+
})
99+
94100
# Leds -------------------------------------------------------------------------------------
95101
if with_led_chaser:
96102
self.leds = LedChaser(

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