targets: add XCU1525 SDRAM BIST option

Add --with-sdram-bist to enable LiteDRAM generator/checker CSRs on the selected DDRAM channels.

Tested on SQRL XCU1525 with Vivado 2024.1:

- --ddram-channels=0,1 --with-sdram-bist full bitstream builds and programs.

- Route clean; DRC 28 warnings/0 errors. Final timing WNS -0.686 ns, with sys_clk met at +0.676 ns; remaining failing paths are main_crg_clkout1/IDELAYCTRL reset related.

- BIOS calibration and 2 MiB memtest pass on both selected controllers.

- sdram_bist all 1024 1 5 reports sdram 6554/6592 MiB/s and sdram1 6555/6598 MiB/s, 0 total errors.

- sdram_hw_test all 0x0 0x1000000 1024 reports 0 errors.

4-channel follow-up:

- --ddram-channels=all --with-sdram-bist builds/routes at 125 MHz/1000 MT/s, but physical channel 1 is marginal while channels 0/2/3 pass BIST.

- The 100 MHz/800 MT/s build is worse on this board and fails BIST/CPU memtest on all channels.

Author: enjoy-digital

litex_boards/targets/sqrl_xcu1525.py

@@ -150,6 +150,7 @@ def __init__(self, sys_clk_freq=125e6, ddram_channel=0,
         pcie_address_width    = 32,
         with_pcie_dma_status  = False,
         with_pcie_dma_monitor = False,
+        with_sdram_bist       = False,
         with_sata             = False,
         with_ethernet         = False,
         with_etherbone        = False,
@@ -222,6 +223,7 @@ def __init__(self, sys_clk_freq=125e6, ddram_channel=0,
                     channel       = channel,
                     phy_name      = phy_name,
                     ddrctrl_name  = f"ddrctrl{channel}",
+                    with_bist     = with_sdram_bist,
                     cached        = not (0x8000_0000 <= origin < 0x1_0000_0000),
                     l2_cache_size = kwargs.get("l2_size", 8192)
                 )
@@ -341,6 +343,7 @@ def main():
     parser.add_target_argument("--pcie-address-width", default=32, type=int, choices=[32, 64], help="PCIe address width.")
     parser.add_target_argument("--pcie-with-dma-status",  action="store_true",       help="Enable PCIe DMA status CSRs.")
     parser.add_target_argument("--pcie-with-dma-monitor", action="store_true",       help="Enable PCIe DMA monitor CSRs.")
+    parser.add_target_argument("--with-sdram-bist",       action="store_true",       help="Enable LiteDRAM BIST generator/checker on selected DDRAM channels.")
     parser.add_target_argument("--with-ethernet",         action="store_true",       help="Enable Ethernet support over QSFP/SFP.")
     parser.add_target_argument("--with-etherbone",        action="store_true",       help="Enable Etherbone support over QSFP/SFP.")
     parser.add_target_argument("--ethernet-port",  default="qsfp0_sfp0", choices=QSFP_PORTS, help="Ethernet QSFP/SFP port.")
@@ -379,6 +382,7 @@ def main():
         pcie_address_width    = args.pcie_address_width,
         with_pcie_dma_status  = args.pcie_with_dma_status,
         with_pcie_dma_monitor = args.pcie_with_dma_monitor,
+        with_sdram_bist       = args.with_sdram_bist,
         with_sata             = args.with_sata,
         with_ethernet         = args.with_ethernet,
         with_etherbone        = args.with_etherbone,