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targets/efinix_tz170: use common hard DDR integration
Move the TZ170 LPDDR4 controller description to platform data and instantiate the reusable LiteX Efinix DDR core. Keep the board's dedicated 33.33MHz-to-600MHz DDR PLL unchanged while removing the duplicated interface writer and bus adapters. This also lets the default 32-bit Wishbone configuration reach the 33-bit hard controller through the common remapping path and correctly connects native CPU sidebands after memory-bus creation.
1 parent be632e2 commit a7fea51

2 files changed

Lines changed: 27 additions & 172 deletions

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‎litex_boards/platforms/efinix_tz170_j484_dev_kit.py‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,20 @@
206206
),
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]
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209+
# DDR Configuration --------------------------------------------------------------------------------
210+
211+
ddr_config = {
212+
"memory_type" : "LPDDR4",
213+
"memory_density" : "8G",
214+
"clkin_sel" : "CLKIN 2",
215+
"location" : "DDR_0",
216+
"dq_width" : 32,
217+
"physical_rank" : 1,
218+
"data_width" : 512,
219+
"address_width" : 33,
220+
"id_width" : 8,
221+
}
222+
209223
# Platform -----------------------------------------------------------------------------------------
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211225
class Platform(EfinixPlatform):
@@ -215,6 +229,8 @@ class Platform(EfinixPlatform):
215229

216230
def __init__(self, toolchain="efinity"):
217231
EfinixPlatform.__init__(self, "Tz170J484I3", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain, spi_width="4")
232+
self.ddr_config = ddr_config
233+
self.ddr_size = 0x4000_0000 # 1GB.
218234

219235
def create_programmer(self):
220236
return EfinixProgrammer(family=self.family)

‎litex_boards/targets/efinix_tz170_j484_dev_kit.py‎

Lines changed: 11 additions & 172 deletions
Original file line numberDiff line numberDiff line change
@@ -10,17 +10,13 @@
1010

1111
from litex.gen import *
1212

13-
from litex.build.generic_platform import Subsignal, Pins
14-
1513
from litex_boards.platforms import efinix_tz170_j484_dev_kit
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1715
from litex.soc.integration.soc import *
18-
from litex.soc.integration.soc import SoCRegion
1916
from litex.soc.integration.builder import *
2017

21-
from litex.soc.interconnect import axi
22-
2318
from litex.soc.cores.clock.efinix import *
19+
from litex.soc.cores.ram.efinix_ddr import EfinixDDR, add_efinix_ddr
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2521
# CRG ----------------------------------------------------------------------------------------------
2622

@@ -75,149 +71,6 @@ def __init__(self, platform):
7571
pll.create_clkout(None, 600e6, nclkout=4, margin=1e-02) # LPDDR4 ctrl
7672

7773

78-
class EfinixLPDDR4(LiteXModule):
79-
def __init__(self, soc, axi_clk, own_crg=True):
80-
platform = soc.platform
81-
data_width = 512
82-
83-
# DRAM Blocks.
84-
# ------------------
85-
from litex.build.efinix import InterfaceWriterBlock
86-
87-
self.bus = axi_bus = axi.AXIInterface(data_width=data_width, address_width=33, id_width=8)
88-
89-
if own_crg:
90-
self.ddr_crg = _CRG_DDR(platform)
91-
92-
class EfinixDRAMBlock(InterfaceWriterBlock):
93-
@staticmethod
94-
def generate():
95-
name = "ddr_inst1"
96-
ddr_def = "DDR_0"
97-
clkin_sel = "CLKIN 2"
98-
data_width = "32"
99-
physical_rank = "1"
100-
mem_type = "LPDDR4"
101-
mem_density = "8G"
102-
103-
cmd = []
104-
cmd.append('design.create_block("{}", "DDR")'.format(name))
105-
cmd.append('design.set_property("{}", "MEMORY_TYPE", "{}", "DDR")'.format(name, mem_type))
106-
cmd.append('design.set_property("{}", "DQ_WIDTH", "{}", "DDR")'.format(name, data_width))
107-
cmd.append('design.set_property("{}", "MEMORY_DENSITY", "{}", "DDR")'.format(name, mem_density))
108-
cmd.append('design.set_property("{}", "PHYSICAL_RANK", "{}", "DDR")'.format(name, physical_rank))
109-
cmd.append('design.set_property("{}", "CLKIN_SEL", "{}", "DDR")'.format(name, clkin_sel))
110-
111-
cmd.append('design.set_property("{}","TARGET0_EN", "1", "DDR")'.format(name))
112-
cmd.append('design.set_property("{}","TARGET1_EN", "0", "DDR")'.format(name))
113-
114-
cmd.append('design.set_property("{}","AXI0_ARADDR_BUS","ddr0_araddr", "DDR")'.format(name))
115-
cmd.append('design.set_property("{}","AXI0_ARAPCMD_PIN","ddr0_arapcmd", "DDR")'.format(name))
116-
cmd.append('design.set_property("{}","AXI0_ARBURST_BUS","ddr0_arburst", "DDR")'.format(name))
117-
cmd.append('design.set_property("{}","AXI0_ARID_BUS","ddr0_arid", "DDR")'.format(name))
118-
cmd.append('design.set_property("{}","AXI0_ARLEN_BUS","ddr0_arlen", "DDR")'.format(name))
119-
cmd.append('design.set_property("{}","AXI0_ARLOCK_PIN","ddr0_arlock", "DDR")'.format(name))
120-
cmd.append('design.set_property("{}","AXI0_ARQOS_PIN","ddr0_arqos", "DDR")'.format(name))
121-
cmd.append('design.set_property("{}","AXI0_ARREADY_PIN","ddr0_arready", "DDR")'.format(name))
122-
cmd.append('design.set_property("{}","AXI0_ARSIZE_BUS","ddr0_arsize", "DDR")'.format(name))
123-
cmd.append('design.set_property("{}","AXI0_ARSTN_PIN","ddr0_resetn", "DDR")'.format(name))
124-
cmd.append('design.set_property("{}","AXI0_ARVALID_PIN","ddr0_arvalid", "DDR")'.format(name))
125-
cmd.append('design.set_property("{}","AXI0_AWADDR_BUS","ddr0_awaddr", "DDR")'.format(name))
126-
cmd.append('design.set_property("{}","AXI0_AWALLSTRB_PIN","ddr0_awallstrb", "DDR")'.format(name))
127-
cmd.append('design.set_property("{}","AXI0_AWAPCMD_PIN","ddr0_awapcmd", "DDR")'.format(name))
128-
cmd.append('design.set_property("{}","AXI0_AWBURST_BUS","ddr0_awburst", "DDR")'.format(name))
129-
cmd.append('design.set_property("{}","AXI0_AWCACHE_BUS","ddr0_awcache", "DDR")'.format(name))
130-
cmd.append('design.set_property("{}","AXI0_AWCOBUF_PIN","ddr0_awcobuf", "DDR")'.format(name))
131-
cmd.append('design.set_property("{}","AXI0_AWID_BUS","ddr0_awid", "DDR")'.format(name))
132-
cmd.append('design.set_property("{}","AXI0_AWLEN_BUS","ddr0_awlen", "DDR")'.format(name))
133-
cmd.append('design.set_property("{}","AXI0_AWLOCK_PIN","ddr0_awlock", "DDR")'.format(name))
134-
cmd.append('design.set_property("{}","AXI0_AWQOS_PIN","ddr0_awqos", "DDR")'.format(name))
135-
cmd.append('design.set_property("{}","AXI0_AWREADY_PIN","ddr0_awready", "DDR")'.format(name))
136-
cmd.append('design.set_property("{}","AXI0_AWSIZE_BUS","ddr0_awsize", "DDR")'.format(name))
137-
cmd.append('design.set_property("{}","AXI0_AWVALID_PIN","ddr0_awvalid", "DDR")'.format(name))
138-
cmd.append('design.set_property("{}","AXI0_BID_BUS","ddr0_bid", "DDR")'.format(name))
139-
cmd.append('design.set_property("{}","AXI0_BREADY_PIN","ddr0_bready", "DDR")'.format(name))
140-
cmd.append('design.set_property("{}","AXI0_BRESP_BUS","ddr0_bresp", "DDR")'.format(name))
141-
cmd.append('design.set_property("{}","AXI0_BVALID_PIN","ddr0_bvalid", "DDR")'.format(name))
142-
cmd.append('design.set_property("{}","AXI0_CLK_INPUT_PIN","{}", "DDR")'.format(name, axi_clk))
143-
cmd.append('design.set_property("{}","AXI0_CLK_INVERT_EN","0", "DDR")'.format(name))
144-
cmd.append('design.set_property("{}","AXI0_DATA_WIDTH","512", "DDR")'.format(name))
145-
cmd.append('design.set_property("{}","AXI0_RDATA_BUS","ddr0_rdata", "DDR")'.format(name))
146-
cmd.append('design.set_property("{}","AXI0_RID_BUS","ddr0_rid", "DDR")'.format(name))
147-
cmd.append('design.set_property("{}","AXI0_RLAST_PIN","ddr0_rlast", "DDR")'.format(name))
148-
cmd.append('design.set_property("{}","AXI0_RREADY_PIN","ddr0_rready", "DDR")'.format(name))
149-
cmd.append('design.set_property("{}","AXI0_RRESP_BUS","ddr0_rresp", "DDR")'.format(name))
150-
cmd.append('design.set_property("{}","AXI0_RVALID_PIN","ddr0_rvalid", "DDR")'.format(name))
151-
cmd.append('design.set_property("{}","AXI0_WDATA_BUS","ddr0_wdata", "DDR")'.format(name))
152-
cmd.append('design.set_property("{}","AXI0_WLAST_PIN","ddr0_wlast", "DDR")'.format(name))
153-
cmd.append('design.set_property("{}","AXI0_WREADY_PIN","ddr0_wready", "DDR")'.format(name))
154-
cmd.append('design.set_property("{}","AXI0_WSTRB_BUS","ddr0_wstrb", "DDR")'.format(name))
155-
cmd.append('design.set_property("{}","AXI0_WVALID_PIN","ddr0_wvalid", "DDR")'.format(name))
156-
157-
cmd.append('design.set_property("{}","CFG_DONE_PIN", "cfg_done", "DDR")'.format(name))
158-
cmd.append('design.set_property("{}","CFG_RESET_PIN", "cfg_reset", "DDR")'.format(name))
159-
cmd.append('design.set_property("{}","CFG_SEL_PIN", "cfg_sel", "DDR")'.format(name))
160-
cmd.append('design.set_property("{}","CFG_START_PIN", "cfg_start", "DDR")'.format(name))
161-
162-
cmd.append('design.set_property("{}","CTRL_BUSY_PIN","", "DDR")'.format(name))
163-
cmd.append('design.set_property("{}","CTRL_CKE_PIN","", "DDR")'.format(name))
164-
cmd.append('design.set_property("{}","CTRL_CLK_INVERT_EN","0", "DDR")'.format(name))
165-
cmd.append('design.set_property("{}","CTRL_CLK_PIN","", "DDR")'.format(name))
166-
cmd.append('design.set_property("{}","CTRL_CMD_Q_ALMOST_FULL_PIN","", "DDR")'.format(name))
167-
cmd.append('design.set_property("{}","CTRL_DP_IDLE_PIN","", "DDR")'.format(name))
168-
cmd.append('design.set_property("{}","CTRL_INT_PIN","", "DDR")'.format(name))
169-
cmd.append('design.set_property("{}","CTRL_MEM_RST_VALID_PIN","", "DDR")'.format(name))
170-
cmd.append('design.set_property("{}","CTRL_PORT_BUSY_PIN","", "DDR")'.format(name))
171-
cmd.append('design.set_property("{}","CTRL_REFRESH_PIN","", "DDR")'.format(name))
172-
173-
cmd.append('design.assign_resource("{}", "{}","DDR")\n'.format(name, ddr_def))
174-
175-
return '\n'.join(cmd) + '\n'
176-
177-
platform.toolchain.ifacewriter.blocks.append(EfinixDRAMBlock())
178-
179-
# DRAM AXI-Ports.
180-
# --------------
181-
axi_io = platform.add_iface_ios(axi_bus.get_ios("ddr0"))
182-
self.comb += axi_bus.connect_to_pads(axi_io, mode="master")
183-
184-
ios = [(f"ddr0", 0,
185-
Subsignal("arapcmd", Pins(1)),
186-
Subsignal("awallstrb", Pins(1)),
187-
Subsignal("awapcmd", Pins(1)),
188-
Subsignal("awcobuf", Pins(1)),
189-
Subsignal("resetn", Pins(1)),
190-
)]
191-
192-
io = platform.add_iface_ios(ios)
193-
self.comb += [
194-
io.arapcmd.eq(0),
195-
io.awallstrb.eq(getattr(soc.cpu, "mBus_awallStrb", 0)),
196-
io.awapcmd.eq(0),
197-
io.awcobuf.eq(0),
198-
io.resetn.eq(~ResetSignal()),
199-
]
200-
201-
cfgs = [(f"cfg", 0,
202-
Subsignal("start", Pins(1)),
203-
Subsignal("reset", Pins(1)),
204-
Subsignal("sel", Pins(1)),
205-
Subsignal("done", Pins(1)),
206-
)]
207-
208-
cfg = platform.add_iface_ios(cfgs)
209-
self.cfg_state = Signal(1, reset=0)
210-
self.cfg_count = Signal(8, reset=0)
211-
212-
self.comb += [
213-
cfg.sel.eq(0),
214-
cfg.reset.eq(self.cfg_state == 0),
215-
cfg.start.eq(self.cfg_state != 0),
216-
]
217-
218-
self.sync += self.cfg_count.eq(self.cfg_count + (self.cfg_count != 0xFF))
219-
self.sync += self.cfg_state.eq(self.cfg_state | (self.cfg_count == 0xFF))
220-
22174
# BaseSoC ------------------------------------------------------------------------------------------
22275

22376
class BaseSoC(SoCCore):
@@ -234,31 +87,17 @@ def __init__(self, sys_clk_freq=100e6, cpu_clk_freq=175e6, with_spi_flash=False,
23487

23588
# LPDDR4 SDRAM -----------------------------------------------------------------------------
23689
if not self.integrated_main_ram_size:
237-
if hasattr(self.cpu, "add_memory_buses") and hasattr(self.cpu, "cpu_clk"):
238-
axi_clk = self.crg.cd_cpu.clk.name_override
239-
else:
240-
axi_clk = self.crg.cd_sys.clk.name_override
241-
242-
self.ddr = EfinixLPDDR4(self, axi_clk)
243-
axi_bus = self.ddr.bus
244-
245-
soc_region = SoCRegion(
246-
origin = self.mem_map.get("main_ram", None),
247-
size = 0x4000_0000, # 1GB.
248-
mode ="rwx",
90+
self.ddr_crg = _CRG_DDR(platform)
91+
clock_domain = "cpu" if (
92+
hasattr(self.cpu, "add_memory_buses") and
93+
hasattr(self.cpu, "cpu_clk")
94+
) else "sys"
95+
self.ddr = EfinixDDR(
96+
platform = platform,
97+
clock_domain = clock_domain,
98+
**platform.ddr_config,
24999
)
250-
# Use DRAM's target0 port as Main Ram.
251-
if hasattr(self.cpu, "add_memory_buses"):
252-
self.cpu.add_memory_buses(address_width = 32, data_width = axi_bus.data_width)
253-
254-
assert len(self.cpu.memory_buses) == 1
255-
mbus = self.cpu.memory_buses[0]
256-
self.comb +=mbus.connect(axi_bus)
257-
self.bus.add_region("main_ram", soc_region)
258-
else:
259-
axi_lite_bus = axi.AXILiteInterface(data_width=axi_bus.data_width, address_width=axi_bus.address_width)
260-
self.submodules += axi.AXILite2AXI(axi_lite_bus, axi_bus)
261-
self.bus.add_slave("main_ram", axi_lite_bus, soc_region)
100+
add_efinix_ddr(self, self.ddr, size=platform.ddr_size)
262101

263102
# SPI Flash --------------------------------------------------------------------------------
264103
if with_spi_flash:

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