ypcb_00338_1p1: Default to JTAG UART (for CI).

Author: enjoy-digital

litex_boards/targets/ypcb_00338_1p1.py

@@ -70,7 +70,9 @@ def __init__(self, sys_clk_freq=125e6,
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
-        # SoCCore -------------------------------------------------------------------------------
+        # SoCCore ----------------------------------------------------------------------------------
+        if kwargs["uart_name"] == "serial":
+            kwargs["uart_name"] = "jtag_uart"
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on YPCB-00338-1P1", **kwargs)
 
         # DDR3 SDRAM ------------------------------------------------------------------------------