targets: default XCU1525 VexiiRiscv to AXI-Lite bus

Use an AXI-Lite SoC bus by default when the SQRL XCU1525 target is built with VexiiRiscv, while preserving explicit --bus-standard overrides.

Validated with 2-channel and 4-channel full-map dry runs, a 2-channel Vivado 2024.1 full build meeting timing, and board boot over regular UART with both DDR controllers passing BIOS memtest.

Author: enjoy-digital

litex_boards/targets/sqrl_xcu1525.py

@@ -402,6 +402,13 @@ def main():
     parser.add_target_argument("--etherbone-ip",   default="192.168.1.50",    help="Etherbone IP address.")
     parser.add_target_argument("--driver",        action="store_true",        help="Generate PCIe driver.")
     parser.add_target_argument("--with-sata",     action="store_true",        help="Enable SATA support (over SFP2SATA on qsfp0_sfp0).")
+
+    # VexiiRiscv exposes an AXI-Lite peripheral bus, so use AXI-Lite as the
+    # default SoC bus for this CPU while still allowing explicit overrides.
+    if (parser.get_value_from_key("--cpu-type", None) == "vexiiriscv" and
+        parser.get_value_from_key("--bus-standard", None) is None):
+        parser.set_defaults(bus_standard="axi-lite")
+
     args = parser.parse_args()
     if args.with_etherbone and args.eth_dynamic_ip:
         parser.error("--eth-dynamic-ip cannot be used with Etherbone.")