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enjoy-digitalenjoy-digital
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Merge pull request #680 from amhagan/AX7203
alinx_ax7203: Add HDMI support to AX7203 FPGA development board
2 parents 2d28c4d + f53eb67 commit aecc509

2 files changed

Lines changed: 61 additions & 14 deletions

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‎litex_boards/platforms/alinx_ax7203.py‎

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
Subsignal("n", Pins("T4"), IOStandard("DIFF_SSTL15")),
2222
),
2323
("cpu_reset_n", 0, Pins("T6"), IOStandard("LVCMOS15")),
24+
("hdmi_reset_n", 0, Pins("J19"), IOStandard("LVCMOS33")),
2425

2526
("clk148p5", 0,
2627
Subsignal("p", Pins("F6"), IOStandard("LVCMOS33")),
@@ -45,10 +46,24 @@
4546
),
4647

4748
# Leds
48-
("user_led", 0, Pins("B13"), IOStandard("LVCMOS18")),
49-
("user_led", 1, Pins("C13"), IOStandard("LVCMOS18")),
50-
("user_led", 2, Pins("D14"), IOStandard("LVCMOS18")),
51-
("user_led", 3, Pins("D15"), IOStandard("LVCMOS18")),
49+
("user_led", 0, Pins("B13"), IOStandard("LVCMOS33")),
50+
("user_led", 1, Pins("C13"), IOStandard("LVCMOS33")),
51+
("user_led", 2, Pins("D14"), IOStandard("LVCMOS33")),
52+
("user_led", 3, Pins("D15"), IOStandard("LVCMOS33")),
53+
54+
# HDMI Out
55+
("hdmi", 0,
56+
Subsignal("r", Pins("V14 H14 J14 K13 K14 L13 L19 L20")),
57+
Subsignal("g", Pins("K17 J17 L16 K16 L14 L15 M15 M16")),
58+
Subsignal("b", Pins("L18 M18 N18 N19 M20 N20 L21 M21")),
59+
Subsignal("de", Pins("V13")),
60+
Subsignal("clk", Pins("M13")),
61+
Subsignal("vsync", Pins("T14")),
62+
Subsignal("hsync", Pins("T15")),
63+
Subsignal("scl", Pins("E16")),
64+
Subsignal("sda", Pins("F16")),
65+
IOStandard("LVCMOS33")
66+
),
5267

5368
# DDR3 SDRAM
5469
("ddram", 0,

‎litex_boards/targets/alinx_ax7203.py‎

Lines changed: 42 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -23,28 +23,36 @@
2323
from litedram.modules import MT41J256M16
2424
from litedram.phy import s7ddrphy
2525

26+
from litex.soc.cores.video import VideoDVIPHY
27+
from litex.soc.cores.bitbang import I2CMaster
28+
2629
# CRG ----------------------------------------------------------------------------------------------
2730
class _CRG(LiteXModule):
28-
def __init__(self, platform, sys_clk_freq):
31+
def __init__(self, platform, sys_clk_freq, with_video_pll=False):
2932
self.rst = Signal()
3033
self.cd_sys = ClockDomain()
3134
self.cd_sys4x = ClockDomain()
3235
self.cd_sys4x_dqs = ClockDomain()
3336
self.cd_idelay = ClockDomain()
37+
self.cd_hdmi = ClockDomain(reset_less=True)
3438

35-
# Clk.
39+
# Clk/Rst.
3640
clk200 = platform.request("clk200")
41+
clk148p5 = platform.request("clk148p5")
42+
rst_n = platform.request("cpu_reset_n")
43+
hdmi_reset = platform.request("hdmi_reset_n")
3744

3845
# Main PLL.
3946
self.pll = pll = S7PLL(speedgrade=-2)
40-
self.comb += pll.reset.eq(self.rst)
47+
self.comb += pll.reset.eq(~rst_n | ~hdmi_reset | self.rst)
4148
pll.register_clkin(clk200, 200e6)
4249
pll.create_clkout(self.cd_sys, sys_clk_freq)
4350
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
4451
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
4552
pll.create_clkout(self.cd_idelay, 200e6)
53+
pll.create_clkout(self.cd_hdmi, 148.5e6, margin=2e-2)
4654
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
47-
55+
4856
# IDELAY Ctrl.
4957
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
5058

@@ -54,12 +62,13 @@ def __init__(self,
5462
sys_clk_freq = int(200e6),
5563
with_led_chaser = True,
5664
with_pcie = False,
65+
with_video_framebuffer = False,
5766
**kwargs):
5867

5968
platform = alinx_ax7203.Platform()
6069

6170
# CRG --------------------------------------------------------------------------------------
62-
self.crg = _CRG(platform, sys_clk_freq)
71+
self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_framebuffer)
6372

6473
# SoCCore ----------------------------------------------------------------------------------
6574
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ALINX AX7203", **kwargs)
@@ -97,27 +106,50 @@ def __init__(self,
97106
self.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
98107
self.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
99108

109+
# Video ------------------------------------------------------------------------------------
110+
if with_video_framebuffer:
111+
hdmi_pads = platform.request("hdmi")
112+
self.videophy = VideoDVIPHY(hdmi_pads, clock_domain="hdmi")
113+
self.videoi2c = I2CMaster(hdmi_pads)
114+
self.videoi2c.add_init(addr=0x72>>1, init_addr_len=1, init=[
115+
(0x0008, 0x35)
116+
])
117+
118+
self.videoi2c.add_init(addr=0x7A>>1, init_addr_len=1, init=[
119+
(0x002f, 0x00)
120+
])
121+
122+
self.videoi2c.add_init(addr=0x60>>1, init_addr_len=1, init=[
123+
(0x0005, 0x10),
124+
(0x0008, 0x05),
125+
(0x0009, 0x01),
126+
(0x0005, 0x04)
127+
])
128+
self.add_video_colorbars(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
129+
100130
# Leds -------------------------------------------------------------------------------------
101131
if with_led_chaser:
102132
self.leds = LedChaser(
103133
pads = platform.request_all("user_led"),
104134
sys_clk_freq = sys_clk_freq)
105-
135+
106136
# Build --------------------------------------------------------------------------------------------
107137
def main():
108138
from litex.build.parser import LiteXArgumentParser
109139
parser = LiteXArgumentParser(platform=alinx_ax7203.Platform, description="LiteX SoC on ALINX AX7203.")
110-
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
111-
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
112-
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
113-
parser.add_target_argument("--driver", action="store_true", help="Generate drivers.")
140+
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
141+
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
142+
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
143+
parser.add_target_argument("--driver", action="store_true", help="Generate drivers.")
144+
parser.add_target_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
114145

115146
args = parser.parse_args()
116147

117148
soc = BaseSoC(
118149
sys_clk_freq = args.sys_clk_freq,
119150
with_led_chaser = True,
120151
with_pcie = args.with_pcie,
152+
with_video_framebuffer = args.with_video_framebuffer,
121153
**parser.soc_argdict
122154
)
123155

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