targets/slogic16u3: Use RAM-backed boot memory

GW5AT devices do not provide the pROM resource that Gowin can infer from LiteX's default read-only integrated BIOS ROM.

Use a small writable integrated boot memory for the SLogic16U3 target so synthesis maps it as RAM/BRAM instead, while keeping the standard BIOS boot flow. The size is reduced to 32 KiB, which is enough for the current BIOS and avoids using a 128 KiB RAM-backed boot memory on this experimental target.

Author: enjoy-digital

litex_boards/targets/sipeed_slogic16u3.py

@@ -51,6 +51,9 @@ def __init__(self, sys_clk_freq=20.732e6, **kwargs):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
+        # GW5AT has no pROM resource, so implement the boot memory as RAM.
+        kwargs["integrated_rom_size"] = 32 * KILOBYTE
+        kwargs["integrated_rom_mode"] = "rwx"
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sipeed Slogic16U3", **kwargs)
 
 # Build --------------------------------------------------------------------------------------------