Merge pull request #682 from 0xDRRB/master

platforms/hyvision_pcie_opt01_revf.py: Fix J9 pinout. Pin 1 is on the edge of the board.

Author: trabucayre

litex_boards/platforms/hyvision_pcie_opt01_revf.py

@@ -182,15 +182,14 @@
 
 _connectors = [
     ( "J9", {
-        1:  "L24",  2: "M22",
-        3:  "M24",  4: "N24",
-        5:  "N22",  6: "P23",
-        7:  "P24",  8: "R23",
-        9:  "T23", 10: "T24",
-        11: "K25", 12: "K26",
-        13: "M25", 14: "M26",
-        15: "N26", 16: "P26",
-        17: "N26", 18: "P26",
+        1:  "N26",  2: "P26",
+        3:  "M25",  4: "M26",
+        5:  "K25",  6: "K26",
+        7:  "T23",  8: "T24",
+        9:  "P24", 10: "R23",
+        11: "N22", 12: "P23",
+        13: "M24", 14: "N24",
+        15: "L24", 16: "M22",
     })
 ]