Merge pull request #752 from yusefkarim/tang_nano_ibex_regfile_option

litex_boards/targets/sipeed_tang_nano_9k.py: set Ibex platform regfile option to fpga

Author: enjoy-digital

litex_boards/targets/sipeed_tang_nano_9k.py

@@ -66,6 +66,11 @@ def __init__(self, toolchain="gowin", sys_clk_freq=27e6, bios_flash_offset=0x0,
         **kwargs):
         platform = sipeed_tang_nano_9k.Platform(toolchain=toolchain)
 
+        # This GW1NR-9 is tight on LUTs, so build Ibex (when selected) with its
+        # distributed-RAM register file instead of the default flip-flop one,
+        # which overflows the part. Ignored by every other CPU.
+        platform.ibex_regfile = "fpga"
+
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)