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Merge pull request #665 from ciccio-87/myir_myc_j7a100t_initial_support
Added initial support (sdram, sdcard, rgmii ethernet) for MYiR MYC-J7A100T board.
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‎litex_boards/platforms/myir_myc_j7a100t.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Samuele Baisi <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("R4"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("T4"), IOStandard("DIFF_SSTL15"))
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),
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("rst_n", 0, Pins("P15"), IOStandard("LVCMOS33")), # the closest button to the sdcard reader
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# Leds
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("user_led", 0, Pins("H15"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("J15"), IOStandard("LVCMOS33")),
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# # Switches # better to be left alone for now
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# ("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
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# ("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
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# ("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
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# ("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("T18")),
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Subsignal("rx", Pins("R18")),
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IOStandard("LVCMOS33")
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),
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# EEPROM
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("eeprom", 0,
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Subsignal("scl", Pins("K17"), Misc("PULLUP true")),
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Subsignal("sda", Pins("J17"), Misc("PULLUP true")),
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IOStandard("LVCMOS33")
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),
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# SPI SDCard
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("spisdcard", 0,
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Subsignal("mosi", Pins("Y21")),
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Subsignal("miso", Pins("P19")),
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Subsignal("clk", Pins("V20")),
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Subsignal("cs_n", Pins("U18")),
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IOStandard("LVCMOS33"),
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),
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# SDCard
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("sdcard", 0,
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Subsignal("data", Pins("P19 R19 U17 U18")),
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Subsignal("cmd", Pins("Y21")),
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Subsignal("clk", Pins("V20")),
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Subsignal("cd", Pins("AA19")),
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IOStandard("LVCMOS33"),
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),
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# Buttons
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("user_btn", 0, Pins("P17"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("N17"), IOStandard("LVCMOS33")),
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# ("user_btn", 2, Pins("P15"), IOStandard("LVCMOS33")), # used for reset
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# SPIFlash
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("dq", Pins("P22 R22 P21 R21 ")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# single chip, 256 MB
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("ddram", 0,
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Subsignal("a", Pins(
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"V2 Y4 Y3 AB5 AB3 AA4 AA1 AA3 AB1 W2 W5 W1 AB6 Y2 Y1"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AA5 W4 AB7"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y8"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AA8"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA6"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("M6 J4"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"R1 M5 P2 P6 N4 N5 N2 P1 L5 K3 K6 J6 M2 L3 M3 L4",
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),
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IOStandard("SSTL15"),
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),
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Subsignal("dqs_p", Pins("P5 M1"),
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IOStandard("DIFF_SSTL15"),
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),
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Subsignal("dqs_n", Pins("P4 L1"),
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IOStandard("DIFF_SSTL15"),
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),
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Subsignal("clk_p", Pins("T5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("U5"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("Y9"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AB8"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB2"), IOStandard("LVCMOS15")),
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# Misc("SLEW=FAST"),
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),
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# both chips, 512 MB
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("ddram", 1,
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Subsignal("a", Pins(
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"V2 Y4 Y3 AB5 AB3 AA4 AA1 AA3 AB1 W2 W5 W1 AB6 Y2 Y1"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AA5 W4 AB7"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y8"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AA8"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA6"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("M6 J4 H2 B1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"R1 M5 P2 P6 N4 N5 N2 P1 L5 K3 K6 J6 M2 L3 M3 L4",
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"G4 G3 J5 H3 H4 K1 H5 G2 E2 A1 G1 B2 F1 C2 F3 D2",
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),
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IOStandard("SSTL15"),
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),
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Subsignal("dqs_p", Pins("P5 M1 K2 E1"),
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IOStandard("DIFF_SSTL15"),
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),
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Subsignal("dqs_n", Pins("P4 L1 J2 D1"),
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IOStandard("DIFF_SSTL15"),
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),
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Subsignal("clk_p", Pins("T5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("U5"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("Y9"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AB8"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB2"), IOStandard("LVCMOS15")),
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# Misc("SLEW=FAST"),
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),
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# RGMII Ethernet (the first port is the closest to the power switch)
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("eth_clocks", 0,
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Subsignal("rx", Pins("W19")),
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Subsignal("tx", Pins("W20")),
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IOStandard("LVCMOS33"),
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),
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("eth_clocks", 1,
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Subsignal("rx", Pins("Y18")),
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Subsignal("tx", Pins("Y19")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("Y22")),
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Subsignal("mdio", Pins("V17")),
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Subsignal("mdc", Pins("W17")),
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Subsignal("rx_ctl", Pins("V18")),
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Subsignal("rx_data", Pins("U22 V22 T21 U21")),
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Subsignal("tx_ctl", Pins("U20")),
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Subsignal("tx_data", Pins("W21 W22 AA20 AA21")),
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# Subsignal("col", Pins("D17")),
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# Subsignal("crs", Pins("G14")),
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IOStandard("LVCMOS33"),
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),
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("eth", 1,
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Subsignal("rst_n", Pins("AB20")),
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Subsignal("mdio", Pins("P14")),
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Subsignal("mdc", Pins("R14")),
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Subsignal("rx_ctl", Pins("V19")),
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Subsignal("rx_data", Pins("AB21 AB22 AA18 AB18")),
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Subsignal("tx_ctl", Pins("P20")),
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Subsignal("tx_data", Pins("N13 N14 P16 R17")),
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# Subsignal("col", Pins("D17")),
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# Subsignal("crs", Pins("G14")),
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IOStandard("LVCMOS33"),
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),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("R16"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B4")),
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Subsignal("rx_n", Pins("A4")),
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Subsignal("tx_p", Pins("B8")),
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Subsignal("tx_n", Pins("A8"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("R16"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B4 D5")),
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Subsignal("rx_n", Pins("A4 C5")),
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Subsignal("tx_p", Pins("B8 D11")),
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Subsignal("tx_n", Pins("A8 C11"))
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),
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# SFP+
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("gtp_refclk", 0,
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Subsignal("p", Pins("F6")),
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Subsignal("n", Pins("E6"))
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),
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("gtp_refclk", 1,
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Subsignal("p", Pins("F10")),
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Subsignal("n", Pins("E10"))
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),
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("sfp", 0,
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Subsignal("rxp", Pins("B6")),
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Subsignal("rxn", Pins("A6")),
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Subsignal("txp", Pins("B10")),
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Subsignal("txn", Pins("A10")),
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),
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("sfp", 1,
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Subsignal("rxp", Pins("D7")),
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Subsignal("rxn", Pins("C7")),
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Subsignal("txp", Pins("D9")),
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Subsignal("txn", Pins("C9")),
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk", Pins("J21")),
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Subsignal("de", Pins("H19")),
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Subsignal("hsync", Pins("J19")),
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Subsignal("vsync", Pins("J20")),
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Subsignal("scl", Pins("L19"), Misc("PULLUP true")),
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Subsignal("sda", Pins("L20"), Misc("PULLUP true")),
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Subsignal("rst_n", Pins("K18")),
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Subsignal("r", Pins("L18 M18 N18 N19 N20 M20 K13 K14")),
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Subsignal("g", Pins("H17 H18 J22 H22 H20 G20 K21 K22")),
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Subsignal("b", Pins("H13 G13 G15 G16 J14 H14 G17 G18")),
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Subsignal("int", Pins("K19"), Misc("PULLUP true")),
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IOStandard("LVCMOS33"),
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),
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# HDMI In
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("hdmi_in", 0,
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Subsignal("clk", Pins("C19")),
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Subsignal("de", Pins("C18")),
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Subsignal("hsync", Pins("C17")),
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Subsignal("vsync", Pins("D12")),
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Subsignal("scl", Pins("E22"), Misc("PULLUP true")),
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Subsignal("sda", Pins("D22"), Misc("PULLUP true")),
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Subsignal("rst_n", Pins("F15")),
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Subsignal("r", Pins("A13 A14 B20 A20 A18 A19 D20 C20")),
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Subsignal("g", Pins("E13 E14 D14 D15 C13 B13 A15 A16")),
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Subsignal("b", Pins("F13 F14 F16 E17 C14 C15 E16 D16")),
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Subsignal("int", Pins("F21")),
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IOStandard("LVCMOS33"),
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)
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
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device = "xc7a100tfgg484-1"
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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[
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property CONFIG_MODE SPIx4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return VivadoProgrammer(flash_part='mx25l25673g-spi-x1_x2_x4')
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 5e8/100e6)

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