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Added Arrow AXE5000 target (Altera Agilex 5 A5EC008BM16AE6S)
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‎README.md‎

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@@ -108,6 +108,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── antmicro_lpddr4_test_board
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├── antmicro_sdi_mipi_video_converter
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├── arduino_mkrvidor4000
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├── arrow_axe5000
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├── avalanche
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├── avnet_aesku40
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├── berkeleylab_marblemini

‎litex_boards/platforms/arrow_axe5000.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Gwenhael Goavec-merou<[email protected]>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk25", 0, Pins("A7"), IOStandard("1.3-V LVCMOS")),
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("refclk", 0, Pins("AJ28"), IOStandard("3.3-V LVCMOS")),
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("sys_clk100", 0, Pins("BF111"), IOStandard("1.3-V LVCMOS")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("AG23")),
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Subsignal("tx", Pins("AG24")),
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IOStandard("3.3-V LVCMOS"),
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),
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# Leds
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("user_led", 0, Pins("AG21"), IOStandard("3.3-V LVCMOS")),
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("rgb_led", 0,
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Subsignal("r", Pins("AH22")),
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Subsignal("g", Pins("AK21")),
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Subsignal("b", Pins("AK20")),
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IOStandard("3.3-V LVCMOS"),
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),
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# Switches
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("user_sw", 0, Pins("A14"), IOStandard("1.3-V LVCMOS")),
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("user_sw", 1, Pins("A13"), IOStandard("1.3-V LVCMOS")),
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# Buttons
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("user_btn", 0, Pins("A12"), IOStandard("1.3-V LVCMOS"), Misc("WEAK_PULL_UP_RESISTOR ON")),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("C3 C2 B4 B6 D3 A4 B3 C6")),
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Subsignal("rwds", Pins("A6")),
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Subsignal("cs_n", Pins("D8")),
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Subsignal("rst_n", Pins("F7")),
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Subsignal("clk", Pins("D7")),
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IOStandard("1.3-V LVCMOS")
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),
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# VADJ selector between 1.2V(low) and 1.3V(high)
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("vsel_1v3", 0, Pins("AJ24"), IOStandard("3.3-V LVCMOS")),
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# Accelerometer (LIS3DH)
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("accel_int", 0, Pins("AK24 AJ25"), IOStandard("3.3-V LVCMOS")),
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("accel_i2c", 0,
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Subsignal("sda", Pins("AK26")),
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Subsignal("scl", Pins("AH25")),
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IOStandard("3.3-V LVCMOS"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Arduino MKR Header (J1/J2)
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("arduino_io", {
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# J1
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"AREF" : "AF22", # 1
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"AIN0" : "AF23", # 2
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"AIN1" : "AF24", # 3
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"AIN2" : "AG26", # 4
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"AIN3" : "AH28", # 5
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"AIN4" : "AH27", # 6
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"AIN5" : "AF27", # 7
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"AIN6" : "AF26", # 8
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"D0" : "AE25", # 9
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"D1" : "AF21", # 10
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"D2" : "AH20", # 11
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"D3" : "AG19", # 12
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"D4" : "AF19", # 13
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"D5" : "AG20", # 14
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# J2
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"D6" : "AK19", # 1
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"D7" : "AJ19", # 2
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"D8" : "AH21", # 3
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"D9" : "AH18", # 4
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"D10" : "AJ20", # 5
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"D11" : "AJ22", # 6 / Also Connected to AK25
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"D12" : "AK22", # 7 / Also Connected to AK27
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"D13" : "AH23", # 8
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"D14" : "AJ23", # 9
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"RST" : "---", # 10
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"GND" : "---", # 11
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"3_3V" : "---", # 12
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"VIN" : "---", # 13
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"5V" : "---", # 14
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}),
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# CRUVI header
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["J3",
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# B2_P/B2_N (27/29) are assigned to 2 sets of pins on the FPGA
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# due to MIPI Hard IP pin placement:
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# B2_P: U5/T4
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# B2_N: AC6/AC5
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# -----------------------------------------------------------
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" ----", # 0
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# NC 3.3V 3.3V ( 1-10).
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" ---- N7 AH26 ---- AJ29 N6 AJ27 AF1 ---- AE10",
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# GND GND GND GND (11-20).
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" AJ28 ---- ---- N2 V6 N1 W5 ---- ---- R2",
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# GND GND T4 AC5 GND (21-30).
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" AC7 T1 AD7 ---- ---- T2 U5 U1 AC6 ----",
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# GND VADJ GND (31-40).
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" ---- V1 V3 V2 W3 ---- ---- T3 U4 R4",
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# GND GND GND GND GND NC (41-50).
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" U3 ---- ---- Y1 P5 W2 P4 ---- ---- ----",
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# NC NC NC GND NC NC NC NC NC 5V (51-60).
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" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
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],
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="quartus"):
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AlteraPlatform.__init__(self, "A5EC008BM16AE6S", _io, _connectors, toolchain=toolchain)
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self.create_rbf = True
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self.create_svf = False # Not supported for Agilex5 family.
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self.add_platform_command("set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS \"ON\"")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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def create_programmer(self):
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return USBBlaster(cable_name="USB Blaster III")
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)

‎litex_boards/targets/arrow_axe5000.py‎

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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Gwenhael Goavec-merou<[email protected]>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import arrow_axe5000
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import Agilex5PLL
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from litex.soc.cores.hyperbus import HyperRAM
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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# # #
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# Clk / Rst
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clk25 = platform.request("clk25")
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rst_n = platform.request("user_btn", 0)
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# Power on reset
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ninit_done = Signal()
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self.specials += Instance("altera_agilex_config_reset_release_endpoint", o_conf_reset = ninit_done)
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# PLL
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self.pll = pll = Agilex5PLL(speedgrade="-6S")
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self.comb += pll.reset.eq(ninit_done | ~rst_n)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# HyperRAM
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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with_l2_cache = False,
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with_led_chaser = True,
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**kwargs):
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platform = arrow_axe5000.Platform()
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# Select 1.3V, for HSIO on CRUVI-HS
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self.comb += platform.request("vsel_1v3").eq(0b1)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arrow AXE5000", **kwargs)
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# HyperRAM ---------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# HyperRAM Parameters.
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hyperram_size = 16 * MEGABYTE
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hyperram_cache_size = 16 * KILOBYTE
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# HyperRAM Bus/Slave Interface.
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hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.bus.add_slave(
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name = "main_ram",
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slave = hyperram_bus,
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region = SoCRegion(origin=self.mem_map["main_ram"], size=hyperram_size, mode="rwx")
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)
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# HyperRAM L2 Cache.
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if with_l2_cache:
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hyperram_cache = wishbone.Cache(
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cachesize = hyperram_cache_size // 4,
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master = hyperram_bus,
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slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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)
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self.hyperram_cache = FullMemoryWE()(hyperram_cache)
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self.add_config("L2_SIZE", hyperram_cache_size)
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# HyperRAM Core.
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self.hyperram = HyperRAM(
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pads = platform.request("hyperram"),
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latency = 7,
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latency_mode = "variable",
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sys_clk_freq = sys_clk_freq,
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clk_ratio = "2:1", # Not working with 4:1
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)
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if with_l2_cache:
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self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
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else:
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self.comb += hyperram_bus.connect(self.hyperram.bus)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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led_pads = platform.request_all("user_led")
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rgb_led_pads = platform.request("rgb_led", 0)
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self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds.
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self.leds = LedChaser(
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pads = Cat(led_pads, rgb_led_pads.r),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=arrow_axe5000.Platform, description="LiteX SoC on Arrow AXE5000.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-l2-cache", action="store_true", help="Enable Main RAM L2 cache.")
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# Overrides defaults synth/conv tools.
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parser.set_defaults(synth_tool = "quartus_syn")
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parser.set_defaults(conv_tool = "quartus_pfg")
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# soc.json default path
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_l2_cache = args.with_l2_cache,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()

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