Merge pull request #774 from trabucayre/radiona_ulx4m_ld

targets/radiona_ulx4m_ld_v2: Disable DDR3 DM

Author: enjoy-digital

litex_boards/targets/radiona_ulx4m_ld_v2.py

@@ -147,16 +147,21 @@ def __init__(self, revision="0.3", device="85F", toolchain="trellis", sys_clk_fr
                 "MT41K512M16": MT41K512M16,
             }
             sdram_module = available_sdram_modules.get(sdram_device)
+            l2_cache_size = kwargs.get("l2_size", 8192)
+            if not l2_cache_size:
+                raise ValueError("ULX4M-LD DDR3 requires an L2 cache when DM is disabled.")
 
             self.submodules.ddrphy = ECP5DDRPHY(
-                pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
-                sys_clk_freq=sys_clk_freq)
+                pads         = PHYPadsReducer(platform.request("ddram"), [0, 1]),
+                sys_clk_freq = sys_clk_freq,
+                with_dm      = False,
+            )
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
                 module        = sdram_module(sys_clk_freq, "1:4"),
-                l2_cache_size = kwargs.get("l2_size", 8192)
+                l2_cache_size = l2_cache_size,
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------