platforms: add Logicbone high-speed IOs

USB3 and PCIe SERDES pinouts taken from the public Logicbone KiCad design files, including fpga-serdes.sch and logicbone.kicad_pcb.

Source: https://github.com/oskirby/logicbone

Author: enjoy-digital

litex_boards/platforms/logicbone.py

@@ -71,6 +71,51 @@
         IOStandard("LVCMOS33")
     ),
 
+    # USB3 / PCIe SERDES
+    ("serdes_clk", 0,
+        Subsignal("p", Pins("Y19")),
+        Subsignal("n", Pins("W20")),
+    ),
+    ("usb3", 0,
+        Subsignal("tx_p", Pins("W4")),
+        Subsignal("tx_n", Pins("W5")),
+        Subsignal("rx_p", Pins("Y5")),
+        Subsignal("rx_n", Pins("Y6")),
+    ),
+    ("usb3", 1,
+        Subsignal("tx_p", Pins("W8")),
+        Subsignal("tx_n", Pins("W9")),
+        Subsignal("rx_p", Pins("Y7")),
+        Subsignal("rx_n", Pins("Y8")),
+    ),
+    ("pcie_x1", 0,
+        Subsignal("rst_n", Pins("M17"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("Y19")),
+        Subsignal("clk_n", Pins("W20")),
+        Subsignal("rx_p",  Pins("Y14")),
+        Subsignal("rx_n",  Pins("Y15")),
+        Subsignal("tx_p",  Pins("W13")),
+        Subsignal("tx_n",  Pins("W14")),
+    ),
+    ("pcie_x1", 1,
+        Subsignal("rst_n", Pins("N19"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("Y19")),
+        Subsignal("clk_n", Pins("W20")),
+        Subsignal("rx_p",  Pins("Y16")),
+        Subsignal("rx_n",  Pins("Y17")),
+        Subsignal("tx_p",  Pins("W17")),
+        Subsignal("tx_n",  Pins("W18")),
+    ),
+    ("pcie_x2", 0,
+        Subsignal("rst_n", Pins("M17"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("Y19")),
+        Subsignal("clk_n", Pins("W20")),
+        Subsignal("rx_p",  Pins("Y14 Y16")),
+        Subsignal("rx_n",  Pins("Y15 Y17")),
+        Subsignal("tx_p",  Pins("W13 W17")),
+        Subsignal("tx_n",  Pins("W14 W18")),
+    ),
+
     # Serial
     ("serial", 0,
         Subsignal("rx", Pins("B6"), IOStandard("LVCMOS33")),