targets/efinix: strip Trion T120 SDRAM AXI origins

The Trion T120 SDRAM AXI ports expose local 256MiB address windows while the SoC decodes them at 0x40000000 and 0x50000000.

Use strip_origin when registering the target ports so the SoC decodes the global regions and the local AXI-Lite ports receive offset addresses.

Author: enjoy-digital

litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py

@@ -370,7 +370,12 @@ def generate(root, namespaces):
                 # Connect AXI interface to the main bus of the SoC.
                 axi_lite_port = axi.AXILiteInterface(data_width=data_width, address_width=28)
                 self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
-                self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000)) # 256MB.
+                self.bus.add_slave(
+                    f"target{n}",
+                    axi_lite_port,
+                    SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000), # 256MB.
+                    strip_origin=True,
+                )
 
             # Use DRAM's target0 port as Main Ram  -----------------------------------------------------
             self.bus.add_region("main_ram", SoCRegion(