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Merge pull request #632 from andelf/feat/add-lckfb-ljpi-support
lckfb_ljpi: Add support for LCKFB LJPI
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‎litex_boards/platforms/lckfb_ljpi.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Andelf <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# LCKFB LJPI FPGA board: https://wiki.lckfb.com/zh-hans/fpga-ljpi/
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.gowin.programmer import GowinProgrammer, GOWIN_CABLE_FT2CH
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("T7"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("F12")),
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Subsignal("rx", Pins("F13")),
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IOStandard("LVCMOS33")
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),
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# Leds. LED2 and LED3 are RGB LEDs.
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("led", 0, Pins( "R9"), IOStandard("LVCMOS33")),
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("led", 1, Pins("C10"), IOStandard("LVCMOS33")),
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("led", 3, Pins( "R7"), IOStandard("LVCMOS33")),
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("led", 2, Pins( "N6"), IOStandard("LVCMOS33")),
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("led", 4, Pins("T10"), IOStandard("LVCMOS33")),
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("led", 5, Pins( "P7"), IOStandard("LVCMOS33")),
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# Buttons. SW2
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("btn_n", 0, Pins("D11"), IOStandard("LVCMOS33")),
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# ("btn_n", 1, Pins("F10"), IOStandard("LVCMOS33")),
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# Reset. Use SW3 as reset button.
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("rst_n", 0, Pins("F10"), IOStandard("LVCMOS33")),
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# SPIFlash.
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# W25Q64JVSSIQ
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("spiflash", 0,
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Subsignal("cs_n", Pins("M9"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("L10"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("R10"), IOStandard("LVCMOS33")),
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),
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# HDMI(LVDS).
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("hdmi", 0,
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Subsignal("clk_p", Pins("M10")),
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Subsignal("clk_n", Pins("N11")),
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Subsignal("data0_p", Pins("R13")),
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Subsignal("data0_n", Pins("T14")),
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Subsignal("data1_p", Pins("R11")),
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Subsignal("data1_n", Pins("T12")),
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Subsignal("data2_p", Pins("R12")),
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Subsignal("data2_n", Pins("P13")),
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IOStandard("LVCMOS33D DRIVE=8"),
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Misc("PULL_MODE=NONE"),
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),
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# 8-segment LED display, Common Anode.
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("seg8", 0, Pins("G13"), IOStandard("LVCMOS33")),
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("seg8", 1, Pins("H16"), IOStandard("LVCMOS33")),
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("seg8", 2, Pins("H12"), IOStandard("LVCMOS33")),
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("seg8", 3, Pins("H13"), IOStandard("LVCMOS33")),
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("seg8", 4, Pins("H14"), IOStandard("LVCMOS33")),
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("seg8", 5, Pins("G12"), IOStandard("LVCMOS33")),
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("seg8", 6, Pins("G11"), IOStandard("LVCMOS33")),
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# ("seg8", 7, Pins("L14"), IOStandard("LVCMOS33")),
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# DDR3 SDRAM
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# MT41J128M16JT-125K.
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("ddram", 0,
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Subsignal("a", Pins("F7 A4 D6 F8 C4 E6 B1 D8 A5 F9 K3 B7 A3 C8"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("H4 D3 H5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("R4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("R6"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L2"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("P5"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G5 F5 F4 F3 E2 C1 E1 B3",
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"M3 K4 N2 L1 P4 H3 R1 M2"),
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IOStandard("SSTL15"),
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Misc("VREF=INTERNAL")),
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Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")),
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Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")),
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Subsignal("clk_p", Pins("J1"), IOStandard("SSTL15D")),
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Subsignal("clk_n", Pins("J3"), IOStandard("SSTL15D")),
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Subsignal("cke", Pins("J2"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("R3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("B9"), IOStandard("SSTL15")),
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),
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# USB Type-C.
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("usb", 0,
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Subsignal("d_p", Pins("M14")),
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Subsignal("d_n", Pins("M15")),
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Subsignal("pullup", Pins("L15")),
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IOStandard("LVCMOS33")
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),
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# Wired to onboard GD32 MCU.
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("mcu_bus", 0,
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Subsignal("data", Pins("PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7"), IOStandard("LVCMOS33"))),
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]
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# Connector IOs ------------------------------------------------------------------------------------
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_connectors = [
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("h5", {
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1: "K16", 2: "J15",
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3: "J14", 4: "J16",
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5: "F14", 6: "F16",
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7: "J13", 8: "H11",
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9: "E16", 10: "F15",
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11: "C16", 12: "D15",
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13: "D16", 14: "E14",
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15: "B13", 16: "A14",
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17: "B14", 18: "A15",
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19: "A12", 20: "B11",
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21: "B12", 22: "C12",
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23: "C11", 24: "A11",
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25: "C9", 26: "A9",
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27: "E10", 28: "D10",
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29: "N10", 30: "M11",
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31: "P12", 32: "P11",
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33: "T13", 34: "T11",
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35: "R14", 36: "T15",
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}),
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("h6", {
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7: "G15", 8: "G14",
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9: "G16", 10: "H15",
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11: "L9",
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13: "L8", 14: "N9",
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15: "M6", 16: "M8",
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17: "M7", 18: "T6",
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19: "N7", 20: "N8",
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21: "P6", 22: "R8",
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23: "T9", 24: "P9",
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25: "T8", 26: "P8",
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27: "K14", 28: "K15",
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29: "K13", 30: "K12",
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31: "N15", 32: "P16",
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33: "P15", 34: "R16",
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35: "N16", 36: "N14",
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}),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="gowin"):
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GowinPlatform.__init__(self, "GW2A-LV18PG256C8/I7", _io, _connectors, toolchain=toolchain, devicename="GW2A-18C")
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self.toolchain.options["use_mspi_as_gpio"] = 1
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self.toolchain.options["use_sspi_as_gpio"] = 1
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def create_programmer(self, kit="openfpgaloader"):
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if kit == "gowin":
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# The board provides an external programmer with an emulated FT2232
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return GowinProgrammer(self.devicename, cable=GOWIN_CABLE_FT2CH)
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else:
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return OpenFPGALoader(cable="ft2232")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

‎litex_boards/targets/lckfb_ljpi.py‎

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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Andelf <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.soc.cores.clock.gowin_gw2a import GW2APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.video import *
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from litex_boards.platforms import lckfb_ljpi
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from litedram.modules import MT41J128M16
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from litedram.phy import GW2DDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_hdmi=False, with_dram=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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if with_dram:
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self.cd_init = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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if with_hdmi:
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk50 = platform.request("clk50")
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rst_n = platform.request("rst_n")
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# Power on reset (the onboard POR is not aware of reprogramming)
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk50)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | ~rst_n)
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pll.register_clkin(clk50, 50e6)
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if with_dram:
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# 2:1 clock needed for DDR
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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self.specials += [
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Instance("DHCEN",
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i_CLKIN = self.cd_sys2x_i.clk,
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i_CE = self.stop,
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o_CLKOUT = self.cd_sys2x.clk),
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Instance("CLKDIV",
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p_DIV_MODE = "2",
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i_CALIB = 0,
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i_HCLKIN = self.cd_sys2x.clk,
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i_RESETN = ~self.reset,
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o_CLKOUT = self.cd_sys.clk),
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]
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# Init clock domain
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self.comb += self.cd_init.clk.eq(clk50)
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self.comb += self.cd_init.rst.eq(pll.reset)
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else:
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset)
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# Video PLL
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if with_hdmi:
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self.video_pll = video_pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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video_pll.register_clkin(clk50, 50e6)
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video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=1e-3)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE = "5",
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i_RESETN = 1, # Disable reset signal.
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i_CALIB = 0, # No calibration.
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i_HCLKIN = self.cd_hdmi5x.clk,
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="gowin", sys_clk_freq=50e6,
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with_spi_flash = False,
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with_led_chaser = True,
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with_buttons = True,
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with_video_terminal = False,
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with_video_colorbars = False,
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**kwargs):
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platform = lckfb_ljpi.Platform(toolchain=toolchain)
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with_hdmi = with_video_terminal or with_video_colorbars
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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assert not (toolchain == "apicula" and with_dram)
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self.crg = _CRG(platform, sys_clk_freq, with_hdmi=with_hdmi, with_dram=with_dram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LCKFB LJPI", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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# if not self.integrated_main_ram_size:
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if with_dram:
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self.ddrphy = GW2DDRPHY(
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pads = platform.request("ddram"),
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sys_clk_freq = sys_clk_freq
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)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64JV as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Video ------------------------------------------------------------------------------------
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if with_hdmi:
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hdmi_pads = platform.request("hdmi")
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self.videophy = VideoHDMIPHY(hdmi_pads, clock_domain="hdmi")
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if with_video_terminal:
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# self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@75Hz", clock_domain="hdmi")
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if with_video_colorbars:
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# self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# self.add_video_colorbars(phy=self.videophy, timings="800x600@75Hz", clock_domain="hdmi")
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self.add_video_colorbars(phy=self.videophy, timings="1024x768@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led"),
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sys_clk_freq = sys_clk_freq
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn_n"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=lckfb_ljpi.Platform, description="LiteX SoC on LCKFB LJPI.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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parser.add_target_argument("--prog-kit", default="gpwin", help="Programmer select from Gowin/openFPGALoader.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_video_colorbars = args.with_video_colorbars,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"))
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if __name__ == "__main__":
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main()

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