targets/sipeed: Align GW5 DDR system clocks

GW5DDRPHY uses sys as the primitive PCLK and sys2x as FCLK. The PHY initialization sequence stops and restarts sys2x, but the GW5 targets generated sys from a separate PLL output. This did not preserve a deterministic PCLK/FCLK relationship across initialization.

Generate only sys2x from the PLL when DDR3 is enabled, gate it with DHCE, and derive sys through a resettable divide-by-two CLKDIV. This matches the working GW2 targets and Gowin's GW5 DDR reference clock topology. Non-DDR configurations keep their direct PLL-generated sys clock.

Author: enjoy-digital

litex_boards/targets/sipeed_tang_console.py

@@ -73,7 +73,11 @@ def __init__(self, platform, sys_clk_freq,
             self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
             self.comb += pll.reset.eq(~por_done | rst)
             pll.register_clkin(clk50, 50e6)
-            pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
+            if with_ddr3:
+                # Keep sys/sys2x phase-aligned across the PHY stop/reset sequence.
+                pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+            else:
+                pll.create_clkout(self.cd_sys, sys_clk_freq)
 
             # SDRAM clock
             if with_sdram:
@@ -88,13 +92,19 @@ def __init__(self, platform, sys_clk_freq,
 
         # DDR3 clock
         if with_ddr3:
-            pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
             self.specials += [
                 Instance("DHCE",
                     i_CLKIN  = self.cd_sys2x_i.clk,
                     i_CEN    = self.stop,
                     o_CLKOUT = self.cd_sys2x.clk
                 ),
+                Instance("CLKDIV",
+                    p_DIV_MODE = "2",
+                    i_CALIB    = 0,
+                    i_HCLKIN   = self.cd_sys2x.clk,
+                    i_RESETN   = ~self.reset,
+                    o_CLKOUT   = self.cd_sys.clk
+                ),
                 AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
             ]
             # Init clock domain

litex_boards/targets/sipeed_tang_mega_138k.py

@@ -81,7 +81,11 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0,
         self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
         self.comb += pll.reset.eq(~por_done | self.rst)
         pll.register_clkin(clk50, 50e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
+        if with_ddr3:
+            # Keep sys/sys2x phase-aligned across the PHY stop/reset sequence.
+            pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        else:
+            pll.create_clkout(self.cd_sys, sys_clk_freq)
         if cpu_clk_freq:
             pll.create_clkout(self.cd_cpu, cpu_clk_freq, with_reset=False)
         platform.toolchain.additional_cst_commands.append("INS_LOC \"PLL\" PLL_R[0]") # Magic incantation for Gowin-AE350 CPU :)
@@ -99,13 +103,19 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0,
 
         # DDR3 clock
         if with_ddr3:
-            pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
             self.specials += [
                 Instance("DHCE",
                     i_CLKIN  = self.cd_sys2x_i.clk,
                     i_CEN    = self.stop,
                     o_CLKOUT = self.cd_sys2x.clk
                 ),
+                Instance("CLKDIV",
+                    p_DIV_MODE = "2",
+                    i_CALIB    = 0,
+                    i_HCLKIN   = self.cd_sys2x.clk,
+                    i_RESETN   = ~self.reset,
+                    o_CLKOUT   = self.cd_sys.clk
+                ),
                 AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
             ]
             # Init clock domain

litex_boards/targets/sipeed_tang_mega_138k_pro.py

@@ -76,7 +76,11 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0,
         self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
         self.comb += pll.reset.eq(~por_done | rst)
         pll.register_clkin(clk50, 50e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
+        if with_ddr3:
+            # Keep sys/sys2x phase-aligned across the PHY stop/reset sequence.
+            pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        else:
+            pll.create_clkout(self.cd_sys, sys_clk_freq)
         if cpu_clk_freq:
             pll.create_clkout(self.cd_cpu, cpu_clk_freq, with_reset=False)
         platform.toolchain.additional_cst_commands.append("INS_LOC \"PLL\" PLL_R[0]") # Magic incantation for Gowin-AE350 CPU :)
@@ -94,13 +98,19 @@ def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0,
 
         # DDR3 clock
         if with_ddr3:
-            pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
             self.specials += [
                 Instance("DHCE",
                     i_CLKIN  = self.cd_sys2x_i.clk,
                     i_CEN    = self.stop,
                     o_CLKOUT = self.cd_sys2x.clk
                 ),
+                Instance("CLKDIV",
+                    p_DIV_MODE = "2",
+                    i_CALIB    = 0,
+                    i_HCLKIN   = self.cd_sys2x.clk,
+                    i_RESETN   = ~self.reset,
+                    o_CLKOUT   = self.cd_sys.clk
+                ),
                 AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
             ]
             # Init clock domain