Efinix Ti180J484 serial port stops printing.

[liqihong8]

I am imitating efinix_ti375_c529_dev-kit to write code related to Ti180J484, trying to make Ti180J484 work properly, but the serial port is stuck in SRAM and not running backwards. I have uploaded the target source code. Serial port printing is as follows:
__ _ __ _ __
/ / () /___ | |//
/ /__/ / __/ -)> <
///_/_//|_|
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BIOS built on Apr 13 2025 19:44:15
BIOS CRC passed (7c4329e0)

LiteX git sha1: 48e65c199

--=============== SoC ==================--
CPU: VexiiRiscv 64-bit @ 50MHz
BUS: axi-lite 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM:
The build command I used is as follows:
litex-boards/litex_boards/targets/efinix_ti180_j484_zyj.py --cpu-type=vexiiriscv --cpu-variant=debian --update-repo=no --with-coherent-dma --vexii-args="--fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --relaxed-div" --l2-bytes=524288 --sys-clk-freq 50000000 --cpu-clk-freq 100000000 --with-cpu-clk --bus-standard axi-lite --cpu-count=1 --build

efinix_ti180_j484_zyj.py.txt

[liqihong8]

The startup process is shown in the figure, and the content after SRAM: has not been printed out.