clk should be removed in platforms/digilent_arty_s7.py

[yhzhang0128]

The Arty S7 board needs STARTUPE2 to access the SPIFlash clock, so the following 2 lines should be removed

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_arty_s7.py#L75
https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_arty_s7.py#L84

This would allow the code to enter this if branch (https://github.com/litex-hub/litespi/blob/master/litespi/clkgen.py#L105) and thus use STARTUPE2 for the Arty S7 board.

Before removing the 2 clk, I was not able to read the SPIFlash in litex bios (with the mem_read command of https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/bios). After removing them, I am able to do that.