No/Invalid HDMI output from Decklink Mini Monitor 4K

[cfib]

I get no picture ("no signal") on two different HDMI monitors from an unmodified DeckLink Mini Monitor 4K when running

decklink_mini_4k.py --with-video-framebuffer --build --load

from 061d12f using Vivado 2025.2 (same result with 2019.1, tough).

I had to add the following line to make Vivado synthesis work:

--- a/litex_boards/targets/decklink_mini_4k.py
+++ b/litex_boards/targets/decklink_mini_4k.py
@@ -46,6 +46,7 @@ class _CRG(LiteXModule):
         clk100 = platform.request("clk100")
         platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
         platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets s7pll0_clkin]")
+        platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets s7pll0_clkin_signal]")
 
         # Main PLL.
         self.pll = pll = S7PLL(speedgrade=-1)

I can connect to the SoC using the JTAG serial console, and everything seems to work fine (see console.log) from that end. Manually writing '1' to the VTG CSR does not lead to a picture on the monitor.

I noticed that Vivado does not manage to generate a 148.5 MHz clock (see also vivado.log):

Clock             Waveform(ns)         Period(ns)      Frequency(MHz)
-----             ------------         ----------      --------------
clk100            {0.000 5.000}        10.000          100.000         
  s7pll0_clkout0  {0.000 3.390}        6.780           147.500         
  s7pll0_clkout1  {0.000 0.847}        1.695           590.000         
  s7pll0_clkout2  {0.424 1.271}        1.695           590.000         
  s7pll0_clkout3  {0.000 2.542}        5.085           196.667         
  s7pll0_clkout4  {0.000 3.390}        6.780           147.500         
  s7pll0_pll_fb   {0.000 25.000}       50.000          20.000          
  s7pll1_pll_fb   {0.000 5.000}        10.000          100.000         

I have also attached decklink_mini_4k_route.dcp.zip (rename to just xxx.dcp to open with Vivado)

[enjoy-digital]

I investigated the generated clocks and found a concrete problem in the current CRG.

The 100MHz input was driving a single integer S7 PLL that was asked to generate 148.5MHz for the system/HDMI domains, 594MHz for DDR3, and 200MHz for IDELAY. This combination is not representable by that PLL. Vivado therefore selected 147.5MHz, 590MHz, and 196.667MHz respectively. The HDMI timing was consequently outside the requested 1080p60 clock rate, and the IDELAY clock did not match the IDELAYE2 200MHz reference-frequency setting.

I opened #764 with the fix in commit 27032c7b:

• the clock-capable 24MHz input and an MMCM now generate exact 148.5MHz and 594MHz clocks;
• the 100MHz input and an auxiliary PLL generate exact 200MHz IDELAY and 150MHz SATA clocks;
• the stale hard-coded PLL net constraints are replaced with a constraint that follows the generated net name.

I tested default and framebuffer elaboration, then ran Vivado 2025.2 through synthesis, placement, and routing. The design routes completely and meets timing with +0.170ns setup WNS and +0.065ns hold WHS. The IDELAY reference-frequency mismatch is no longer reported.

@cfib, could you test #764 on the board with the same command?

./decklink_mini_4k.py --with-video-framebuffer --build --load

Please report whether the monitor now detects the signal and whether DDR3 initialization/calibration still completes normally. If the exact clock fix does not restore HDMI output, the existing GTP reference-clock path will be the next point to isolate.

[cfib]

HW test results with commit 27032c7:

• Sadly, still no picture via HDMI on my monitors.
• DRAM still works (Memtest OK)

Vivado now reports the correct clock frequencies (148.502 may be due to rounding error), see also vivado.log

Clock             Waveform(ns)         Period(ns)      Frequency(MHz)
-----             ------------         ----------      --------------
clk100            {0.000 5.000}        10.000          100.000         
  s7pll_clkout0   {0.000 2.500}        5.000           200.000         
  s7pll_pll_fb    {0.000 5.000}        10.000          100.000         
clk24             {0.000 20.833}       41.666          24.000          
  s7mmcm_clkout0  {0.000 3.367}        6.734           148.502         
  s7mmcm_clkout1  {0.000 0.842}        1.683           594.009         
  s7mmcm_clkout2  {0.421 1.263}        1.683           594.009         
  s7mmcm_clkout3  {0.000 3.367}        6.734           148.502         
  s7mmcm_mmcm_fb  {0.000 20.833}       41.666          24.000          

I found some warnings regarding the GTPE2_CHANNEL instantiations in the Vivado logs:

WARNING: [Synth 8-689] width (16) of port connection 'TXDATA' does not match port width (32) of module 'GTPE2_CHANNEL' [/home/christian/opt/litex/litex-boards/litex_boards/targets/build/decklink_mini_4k/gateware/decklink_mini_4k.v:30843]

However, having little experience with the GTP blocks, I cannot say how critical they are.

Is there maybe a confirmed working bitstream for the Decklink card that I can test my hardware/setup with?