[Feature Request] Add board target support for Great Scott Gadgets HackRF Pro

[ohault]

🚀 Feature Description

Add a dedicated board target for the HackRF Pro (by Great Scott Gadgets) in litex-boards.

The HackRF Pro replaces the Xilinx CoolRunner-II CPLD found in the classic HackRF One with an open-source-friendly Lattice iCE40 UltraPlus FPGA (iCE40UP5K). Adding LiteX target support will enable developers to build custom open-source SoCs, offload digital signal processing (DSP) tasks, and integrate LiteX-based IP (e.g., Wishbone/AXI interconnects, soft-core processors, UART/USB stream interfaces) directly onto the device.

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🔍 Board Overview & Hardware Specifications

• FPGA: Lattice iCE40 UltraPlus (iCE40UP5K-SG48 / iCE40UP5K-UWG30)
• System Clock / Oscillator: Onboard low-jitter TCXO crystal
• Memory Capabilities:
  • Integrated 1 Mbit SPRAM (ideal for LiteX CPU main memory / instruction cache)
  • Onboard SPI Flash (shared/programmable via primary MCU)
• Primary Toolchain: Open-source yosys + nextpnr-ice40 (Project IceStorm)
• Peripherals & Interfaces connected to FPGA:
  • High-speed parallel/serial interface to primary MCU / USB engine
  • I/Q Transceiver / ADC / DAC control pins
  • SMA trigger and synchronization lines
  • Internal header expansion pins
  • Onboard status LEDs / User IO

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🛠️ Proposed Implementation Plan

A new target module litex_boards/targets/gsg_hackrf_pro.py alongside a platform definition litex_boards/platforms/gsg_hackrf_pro.py would provide:

1. Platform Definition (gsg_hackrf_pro.py)

• Define _io constraints for:
  • System Clock input (TCXO)
  • Baseband I/Q sample bus (ADC/DAC interface)
  • Microcontroller interface bus
  • User LEDs, buttons, and expansion header IOs
• Default toolchain binding to icestorm / yosys / nextpnr-ice40.

2. Base SoC & Clock Generator Target

• Clocking: Instantiate iCE40PLL or drive directly from TCXO depending on desired system frequency (e.g., 12 MHz, 24 MHz, or 48 MHz).
• RAM Integration: Automatically instantiate internal iCE40 SPRAM blocks using standard LiteX SPRAM wrappers to provide ~128 KB of zero-wait-state RAM for soft cores (e.g., VexRiscv-Lite, FemtoRV, or SERV).
• Control & Status: Standard SoCCore functionality with Wishbone bus and optional LiteScope logic analyzer integration for hardware debugging.

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💡 Use Cases & Benefits

1. Custom Hardware DSP Acceleration: Allows developers to write Migen/LiteX cores for real-time SDR tasks (FFTs, decimation/interpolation filters, modulation engines) that stream I/Q samples to/from the radio frontend.
2. Standalone Embedded Operation: Enables running lightweight bare-metal firmware or FreeRTOS on a soft-core RISC-V CPU directly on the HackRF Pro without requiring external host USB control.
3. Fully Open-Source EDA Pipeline: Builds entirely with yosys + nextpnr-ice40, aligning perfectly with LiteX's open-source philosophy.

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📁 References & Prior Art

• Hardware Repository: Great Scott Gadgets - HackRF Hardware & Firmware
• Existing Similar Targets:
  • litex_boards/platforms/icebreaker.py
  • litex_boards/platforms/fomu.py
  • litex_boards/platforms/upduino_v3.py

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🤝 Willingness to Contribute

• I am willing to test this target on physical hardware.
• I can help submit a Pull Request once the official pinout / schematic mapping is verified from the open-source hardware KiCad files.