use sperate pr for CPU convert SIMD compatibility changes

liubo-intel · liubo-intel · commit 4d5e82304de6 · 2025-08-08T05:15:21.000-04:00
diff --git a/src/plugins/intel_cpu/src/nodes/common/cpu_convert.cpp b/src/plugins/intel_cpu/src/nodes/common/cpu_convert.cpp
@@ -73,7 +73,7 @@ template <>
     const auto& f16vec = gen.xmm3;
     const auto& f32vec = gen.ymm4;
 
-    gen.uni_vmovdqu(f16vec, gen.xword[src]);
+    gen.movdqu(f16vec, gen.xword[src]);
     gen.vcvtph2ps(f32vec, f16vec);
     gen.vmovups(gen.yword[dst], f32vec);
 }
@@ -85,7 +85,7 @@ template <>
 
     gen.vmovups(f32vec, gen.yword[src]);
     gen.vcvtps2ph(f16vec, f32vec, 0);
-    gen.uni_vmovdqu(gen.xword[dst], f16vec);
+    gen.movdqu(gen.xword[dst], f16vec);
 }
 
 template <typename src_t, typename dst_t>

Original file line number	Diff line number	Diff line change
`@@ -73,7 +73,7 @@ template <>`
`73`	`73`	`const auto& f16vec = gen.xmm3;`
`74`	`74`	`const auto& f32vec = gen.ymm4;`
`75`	`75`
`76`		`- gen.uni_vmovdqu(f16vec, gen.xword[src]);`
	`76`	`+ gen.movdqu(f16vec, gen.xword[src]);`
`77`	`77`	`gen.vcvtph2ps(f32vec, f16vec);`
`78`	`78`	`gen.vmovups(gen.yword[dst], f32vec);`
`79`	`79`	`}`
`@@ -85,7 +85,7 @@ template <>`
`85`	`85`
`86`	`86`	`gen.vmovups(f32vec, gen.yword[src]);`
`87`	`87`	`gen.vcvtps2ph(f16vec, f32vec, 0);`
`88`		`- gen.uni_vmovdqu(gen.xword[dst], f16vec);`
	`88`	`+ gen.movdqu(gen.xword[dst], f16vec);`
`89`	`89`	`}`
`90`	`90`
`91`	`91`	`template <typename src_t, typename dst_t>`