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CIRGenBuiltinX86.cpp
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1882 lines (1748 loc) · 73.9 KB
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//===---- CIRGenBuiltinX86.cpp - Emit CIR for X86 builtins ----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This contains code to emit x86/x86_64 Builtin calls as CIR or a function
// call to be later resolved.
//
//===----------------------------------------------------------------------===//
#include "CIRGenCXXABI.h"
#include "CIRGenCall.h"
#include "CIRGenFunction.h"
#include "CIRGenModule.h"
#include "TargetInfo.h"
#include "clang/CIR/MissingFeatures.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
#include "mlir/IR/Value.h"
#include "clang/AST/GlobalDecl.h"
#include "clang/Basic/Builtins.h"
#include "clang/Basic/TargetBuiltins.h"
#include "clang/CIR/Dialect/IR/CIRDialect.h"
#include "clang/CIR/Dialect/IR/CIRTypes.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/IR/IntrinsicsX86.h"
#include "llvm/Support/ErrorHandling.h"
using namespace clang;
using namespace clang::CIRGen;
using namespace cir;
static std::optional<CIRGenFunction::MSVCIntrin>
translateX86ToMsvcIntrin(unsigned BuiltinID) {
using MSVCIntrin = CIRGenFunction::MSVCIntrin;
switch (BuiltinID) {
default:
return std::nullopt;
case clang::X86::BI_BitScanForward:
case clang::X86::BI_BitScanForward64:
return MSVCIntrin::_BitScanForward;
case clang::X86::BI_BitScanReverse:
case clang::X86::BI_BitScanReverse64:
return MSVCIntrin::_BitScanReverse;
case clang::X86::BI_InterlockedAnd64:
return MSVCIntrin::_InterlockedAnd;
case clang::X86::BI_InterlockedCompareExchange128:
return MSVCIntrin::_InterlockedCompareExchange128;
case clang::X86::BI_InterlockedExchange64:
return MSVCIntrin::_InterlockedExchange;
case clang::X86::BI_InterlockedExchangeAdd64:
return MSVCIntrin::_InterlockedExchangeAdd;
case clang::X86::BI_InterlockedExchangeSub64:
return MSVCIntrin::_InterlockedExchangeSub;
case clang::X86::BI_InterlockedOr64:
return MSVCIntrin::_InterlockedOr;
case clang::X86::BI_InterlockedXor64:
return MSVCIntrin::_InterlockedXor;
case clang::X86::BI_InterlockedDecrement64:
return MSVCIntrin::_InterlockedDecrement;
case clang::X86::BI_InterlockedIncrement64:
return MSVCIntrin::_InterlockedIncrement;
}
llvm_unreachable("must return from switch");
}
/// Get integer from a mlir::Value that is an int constant or a constant op.
static int64_t getIntValueFromConstOp(mlir::Value val) {
return val.getDefiningOp<cir::ConstantOp>().getIntValue().getSExtValue();
}
// Convert the mask from an integer type to a vector of i1.
static mlir::Value getMaskVecValue(CIRGenFunction &cgf, mlir::Value mask,
unsigned numElts, mlir::Location loc) {
cir::VectorType maskTy =
cir::VectorType::get(cgf.getBuilder().getSIntNTy(1),
cast<cir::IntType>(mask.getType()).getWidth());
mlir::Value maskVec = cgf.getBuilder().createBitcast(mask, maskTy);
// If we have less than 8 elements, then the starting mask was an i8 and
// we need to extract down to the right number of elements.
if (numElts < 8) {
llvm::SmallVector<int64_t, 4> indices;
for (unsigned i = 0; i != numElts; ++i)
indices.push_back(i);
maskVec = cgf.getBuilder().createVecShuffle(loc, maskVec, maskVec, indices);
}
return maskVec;
}
static mlir::Value emitX86MaskedStore(CIRGenFunction &cgf,
ArrayRef<mlir::Value> ops,
llvm::Align alignment,
mlir::Location loc) {
mlir::Value ptr = ops[0];
mlir::Value maskVec = getMaskVecValue(
cgf, ops[2], cast<cir::VectorType>(ops[1].getType()).getSize(), loc);
return cgf.getBuilder().createMaskedStore(loc, ops[1], ptr, alignment,
maskVec);
}
static mlir::Value emitX86MaskedLoad(CIRGenFunction &cgf,
ArrayRef<mlir::Value> ops,
llvm::Align alignment,
mlir::Location loc) {
mlir::Type ty = ops[1].getType();
mlir::Value ptr = ops[0];
mlir::Value maskVec =
getMaskVecValue(cgf, ops[2], cast<cir::VectorType>(ty).getSize(), loc);
return cgf.getBuilder().createMaskedLoad(loc, ty, ptr, alignment, maskVec,
ops[1]);
}
static mlir::Value emitX86ExpandLoad(CIRGenFunction &cgf,
ArrayRef<mlir::Value> ops,
mlir::Location loc) {
auto resultTy = cast<cir::VectorType>(ops[1].getType());
mlir::Value ptr = ops[0];
mlir::Value maskVec = getMaskVecValue(
cgf, ops[2], cast<cir::VectorType>(resultTy).getSize(), loc);
return cir::LLVMIntrinsicCallOp::create(
cgf.getBuilder(), loc,
cgf.getBuilder().getStringAttr("masked.expandload"), resultTy,
mlir::ValueRange{ptr, maskVec, ops[1]})
.getResult();
}
static mlir::Value emitX86CompressStore(CIRGenFunction &cgf,
ArrayRef<mlir::Value> ops,
mlir::Location loc) {
auto resultTy = cast<cir::VectorType>(ops[1].getType());
mlir::Value ptr = ops[0];
mlir::Value maskVec = getMaskVecValue(cgf, ops[2], resultTy.getSize(), loc);
return cir::LLVMIntrinsicCallOp::create(
cgf.getBuilder(), loc,
cgf.getBuilder().getStringAttr("masked.compressstore"),
cgf.getBuilder().getVoidTy(),
mlir::ValueRange{ops[1], ptr, maskVec})
.getResult();
}
static mlir::Value emitX86SExtMask(CIRGenFunction &cgf, mlir::Value op,
mlir::Type dstTy, mlir::Location loc) {
unsigned numberOfElements = cast<cir::VectorType>(dstTy).getSize();
mlir::Value mask = getMaskVecValue(cgf, op, numberOfElements, loc);
return cgf.getBuilder().createCast(loc, cir::CastKind::integral, mask, dstTy);
}
static mlir::Value emitX86PSLLDQIByteShift(CIRGenFunction &cgf,
const CallExpr *E,
ArrayRef<mlir::Value> Ops) {
CIRGenBuilderTy &builder = cgf.getBuilder();
unsigned shiftVal = getIntValueFromConstOp(Ops[1]) & 0xff;
mlir::Location loc = cgf.getLoc(E->getExprLoc());
auto byteVecType = cast<cir::VectorType>(Ops[0].getType());
// Get the original return type from the expression
auto resultType = cast<cir::VectorType>(cgf.convertType(E->getType()));
// If pslldq is shifting the vector more than 15 bytes, emit zero.
// This matches the hardware behavior where shifting by 16+ bytes
// clears the entire 128-bit lane.
if (shiftVal >= 16) {
mlir::Value zero = builder.getZero(loc, byteVecType);
if (byteVecType != resultType)
return builder.createBitcast(zero, resultType);
return zero;
}
// Builtin type is vXi8 (already in bytes)
unsigned numElts = byteVecType.getSize();
assert(numElts % 16 == 0 && "Vector size must be multiple of 16 bytes");
llvm::SmallVector<int64_t, 64> indices;
// 256/512-bit pslldq operates on 128-bit lanes so we need to handle that
for (unsigned l = 0; l < numElts; l += 16) {
for (unsigned i = 0; i != 16; ++i) {
unsigned idx = numElts + i - shiftVal;
if (idx < numElts)
idx -= numElts - 16; // end of lane, switch operand.
indices.push_back(idx + l);
}
}
mlir::Value zero = builder.getZero(loc, byteVecType);
// Perform the shuffle (left shift by inserting zeros)
mlir::Value shuffleResult = builder.createVecShuffle(loc, zero, Ops[0], indices);
// Cast back to original type if necessary
if (byteVecType != resultType)
return builder.createBitcast(shuffleResult, resultType);
return shuffleResult;
}
static mlir::Value emitX86PSRLDQIByteShift(CIRGenFunction &cgf,
const CallExpr *E,
ArrayRef<mlir::Value> Ops) {
CIRGenBuilderTy &builder = cgf.getBuilder();
auto byteVecType = cast<cir::VectorType>(Ops[0].getType());
mlir::Location loc = cgf.getLoc(E->getExprLoc());
unsigned shiftVal = getIntValueFromConstOp(Ops[1]) & 0xff;
// Get the original return type from the expression
auto resultType = cast<cir::VectorType>(cgf.convertType(E->getType()));
// If psrldq is shifting the vector more than 15 bytes, emit zero.
if (shiftVal >= 16) {
mlir::Value zero = builder.getZero(loc, byteVecType);
if (byteVecType != resultType)
return builder.createBitcast(zero, resultType);
return zero;
}
// Builtin type is vXi8 (already in bytes)
uint64_t numElts = byteVecType.getSize();
assert(numElts % 16 == 0 && "Expected a multiple of 16");
llvm::SmallVector<int64_t, 64> indices;
// This correlates to the OG CodeGen
// As stated in the OG, 256/512-bit psrldq operates on 128-bit lanes.
// So we have to make sure we handle it.
for (unsigned l = 0; l < numElts; l += 16) {
for (unsigned i = 0; i < 16; ++i) {
unsigned idx = i + shiftVal;
if (idx >= 16)
idx += numElts - 16;
indices.push_back(idx + l);
}
}
mlir::Value zero = builder.getZero(loc, byteVecType);
// Perform the shuffle (right shift by inserting zeros from the left)
mlir::Value shuffleResult = builder.createVecShuffle(loc, Ops[0], zero, indices);
// Cast back to original type if necessary
if (byteVecType != resultType)
return builder.createBitcast(shuffleResult, resultType);
return shuffleResult;
}
static mlir::Value emitX86MaskedCompareResult(CIRGenFunction &cgf,
mlir::Value cmp, unsigned numElts,
mlir::Value maskIn,
mlir::Location loc) {
if (maskIn) {
llvm_unreachable("NYI");
}
if (numElts < 8) {
int64_t indices[8];
for (unsigned i = 0; i != numElts; ++i)
indices[i] = i;
for (unsigned i = numElts; i != 8; ++i)
indices[i] = i % numElts + numElts;
// This should shuffle between cmp (first vector) and null (second vector)
mlir::Value nullVec = cgf.getBuilder().getNullValue(cmp.getType(), loc);
cmp = cgf.getBuilder().createVecShuffle(loc, cmp, nullVec, indices);
}
return cgf.getBuilder().createBitcast(
cmp, cgf.getBuilder().getUIntNTy(std::max(numElts, 8U)));
}
static mlir::Value emitX86MaskedCompare(CIRGenFunction &cgf, unsigned cc,
bool isSigned,
ArrayRef<mlir::Value> ops,
mlir::Location loc) {
assert((ops.size() == 2 || ops.size() == 4) &&
"Unexpected number of arguments");
unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
mlir::Value cmp;
if (cc == 3) {
llvm_unreachable("NYI");
} else if (cc == 7) {
llvm_unreachable("NYI");
} else {
cir::CmpOpKind pred;
switch (cc) {
default:
llvm_unreachable("Unknown condition code");
case 0:
pred = cir::CmpOpKind::eq;
break;
case 1:
pred = cir::CmpOpKind::lt;
break;
case 2:
pred = cir::CmpOpKind::le;
break;
case 4:
pred = cir::CmpOpKind::ne;
break;
case 5:
pred = cir::CmpOpKind::ge;
break;
case 6:
pred = cir::CmpOpKind::gt;
break;
}
auto resultTy = cgf.getBuilder().getType<cir::VectorType>(
cgf.getBuilder().getUIntNTy(1), numElts);
cmp = cir::VecCmpOp::create(cgf.getBuilder(), loc, resultTy, pred, ops[0],
ops[1]);
}
mlir::Value maskIn;
if (ops.size() == 4)
maskIn = ops[3];
return emitX86MaskedCompareResult(cgf, cmp, numElts, maskIn, loc);
}
static mlir::Value emitX86ConvertToMask(CIRGenFunction &cgf, mlir::Value in,
mlir::Location loc) {
cir::ConstantOp zero = cgf.getBuilder().getNullValue(in.getType(), loc);
return emitX86MaskedCompare(cgf, 1, true, {in, zero}, loc);
}
mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
const CallExpr *E) {
if (BuiltinID == Builtin::BI__builtin_cpu_is)
llvm_unreachable("__builtin_cpu_is NYI");
if (BuiltinID == Builtin::BI__builtin_cpu_supports)
llvm_unreachable("__builtin_cpu_supports NYI");
if (BuiltinID == Builtin::BI__builtin_cpu_init)
llvm_unreachable("__builtin_cpu_init NYI");
// Handle MSVC intrinsics before argument evaluation to prevent double
// evaluation.
if (std::optional<MSVCIntrin> MsvcIntId = translateX86ToMsvcIntrin(BuiltinID))
llvm_unreachable("translateX86ToMsvcIntrin NYI");
llvm::SmallVector<mlir::Value, 4> Ops;
// Find out if any arguments are required to be integer constant expressions.
unsigned ICEArguments = 0;
ASTContext::GetBuiltinTypeError Error;
getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
assert(Error == ASTContext::GE_None && "Should not codegen an error");
for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
Ops.push_back(emitScalarOrConstFoldImmArg(ICEArguments, i, E));
}
// OG has unordered comparison as a form of optimization in addition to
// ordered comparison, while CIR doesn't.
//
// This means that we can't encode the comparison code of UGT (unordered
// greater than), at least not at the CIR level.
//
// The boolean shouldInvert compensates for this.
// For example: to get to the comparison code UGT, we pass in
// getVectorFCmpIR(OLE, shouldInvert = true) since OLE is the inverse of UGT.
// There are several ways to support this otherwise:
// - register extra CmpOpKind for unordered comparison types and build the
// translation code for
// to go from CIR -> LLVM dialect. Notice we get this naturally with
// shouldInvert, benefiting from existing infrastructure, albeit having to
// generate an extra `not` at CIR).
// - Just add extra comparison code to a new VecCmpOpKind instead of
// cluttering CmpOpKind.
// - Add a boolean in VecCmpOp to indicate if it's doing unordered or ordered
// comparison
// - Just emit the intrinsics call instead of calling this helper, see how the
// LLVM lowering handles this.
auto getVectorFCmpIR = [this, &Ops, &E](cir::CmpOpKind pred,
bool shouldInvert, bool isSignaling) {
assert(!cir::MissingFeatures::CGFPOptionsRAII());
auto loc = getLoc(E->getExprLoc());
mlir::Value cmp;
if (builder.getIsFPConstrained())
// TODO: Add isSignaling boolean once emitConstrainedFPCall implemented
assert(cir::MissingFeatures::emitConstrainedFPCall());
else
cmp = builder.createVecCompare(loc, pred, Ops[0], Ops[1]);
mlir::Value bitCast = builder.createBitcast(
shouldInvert ? builder.createNot(cmp) : cmp, Ops[0].getType());
return bitCast;
};
switch (BuiltinID) {
default:
return nullptr;
case X86::BI_mm_prefetch: {
mlir::Value Address = builder.createPtrBitcast(Ops[0], VoidTy);
int64_t Hint = getIntValueFromConstOp(Ops[1]);
mlir::Value RW =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()),
cir::IntAttr::get(SInt32Ty, (Hint >> 2) & 0x1));
mlir::Value Locality =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()),
cir::IntAttr::get(SInt32Ty, Hint & 0x3));
mlir::Value Data = cir::ConstantOp::create(builder, getLoc(E->getExprLoc()),
cir::IntAttr::get(SInt32Ty, 1));
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("prefetch"), voidTy,
mlir::ValueRange{Address, RW, Locality, Data})
.getResult();
}
case X86::BI_mm_clflush: {
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse2.clflush"), voidTy, Ops[0])
.getResult();
}
case X86::BI_mm_lfence: {
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse2.lfence"), voidTy)
.getResult();
}
case X86::BI_mm_pause: {
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse2.pause"), voidTy)
.getResult();
}
case X86::BI_mm_mfence: {
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse2.mfence"), voidTy)
.getResult();
}
case X86::BI_mm_sfence: {
mlir::Type voidTy = cir::VoidType::get(&getMLIRContext());
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse.sfence"), voidTy)
.getResult();
}
case X86::BI__rdtsc: {
mlir::Type intTy = cir::IntType::get(&getMLIRContext(), 64, false);
return cir::LLVMIntrinsicCallOp::create(builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.rdtsc"),
intTy)
.getResult();
}
case X86::BI__builtin_ia32_rdtscp: {
// For rdtscp, we need to create a proper struct type to hold {i64, i32}
cir::RecordType resTy = builder.getAnonRecordTy(
{builder.getUInt64Ty(), builder.getUInt32Ty()}, false, false);
auto call = cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.rdtscp"), resTy)
.getResult();
// Store processor ID in address param
mlir::Value pID = cir::ExtractMemberOp::create(
builder, getLoc(E->getExprLoc()), builder.getUInt32Ty(), call, 1);
cir::StoreOp::create(builder, getLoc(E->getExprLoc()), pID, Ops[0]);
// Return the timestamp at index 0
return cir::ExtractMemberOp::create(builder, getLoc(E->getExprLoc()),
builder.getUInt64Ty(), call, 0);
}
case X86::BI__builtin_ia32_lzcnt_u16:
case X86::BI__builtin_ia32_lzcnt_u32:
case X86::BI__builtin_ia32_lzcnt_u64: {
mlir::Value V =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()),
cir::BoolAttr::get(&getMLIRContext(), false));
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()), builder.getStringAttr("ctlz"),
Ops[0].getType(), mlir::ValueRange{Ops[0], V})
.getResult();
}
case X86::BI__builtin_ia32_tzcnt_u16:
case X86::BI__builtin_ia32_tzcnt_u32:
case X86::BI__builtin_ia32_tzcnt_u64: {
mlir::Value V =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()),
cir::BoolAttr::get(&getMLIRContext(), false));
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()), builder.getStringAttr("cttz"),
Ops[0].getType(), mlir::ValueRange{Ops[0], V})
.getResult();
}
case X86::BI__builtin_ia32_undef128:
case X86::BI__builtin_ia32_undef256:
case X86::BI__builtin_ia32_undef512:
// The x86 definition of "undef" is not the same as the LLVM definition
// (PR32176). We leave optimizing away an unnecessary zero constant to the
// IR optimizer and backend.
// TODO: If we had a "freeze" IR instruction to generate a fixed undef
// value, we should use that here instead of a zero.
return builder.getNullValue(convertType(E->getType()),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_vec_ext_v4hi:
case X86::BI__builtin_ia32_vec_ext_v16qi:
case X86::BI__builtin_ia32_vec_ext_v8hi:
case X86::BI__builtin_ia32_vec_ext_v4si:
case X86::BI__builtin_ia32_vec_ext_v4sf:
case X86::BI__builtin_ia32_vec_ext_v2di:
case X86::BI__builtin_ia32_vec_ext_v32qi:
case X86::BI__builtin_ia32_vec_ext_v16hi:
case X86::BI__builtin_ia32_vec_ext_v8si:
case X86::BI__builtin_ia32_vec_ext_v4di: {
unsigned NumElts = cast<cir::VectorType>(Ops[0].getType()).getSize();
uint64_t index =
Ops[1].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue();
index &= NumElts - 1;
auto indexAttr = cir::IntAttr::get(
cir::IntType::get(&getMLIRContext(), 64, false), index);
auto indexVal =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()), indexAttr);
// These builtins exist so we can ensure the index is an ICE and in range.
// Otherwise we could just do this in the header file.
return cir::VecExtractOp::create(builder, getLoc(E->getExprLoc()), Ops[0],
indexVal);
}
case X86::BI__builtin_ia32_vec_set_v4hi:
case X86::BI__builtin_ia32_vec_set_v16qi:
case X86::BI__builtin_ia32_vec_set_v8hi:
case X86::BI__builtin_ia32_vec_set_v4si:
case X86::BI__builtin_ia32_vec_set_v2di:
case X86::BI__builtin_ia32_vec_set_v32qi:
case X86::BI__builtin_ia32_vec_set_v16hi:
case X86::BI__builtin_ia32_vec_set_v8si:
case X86::BI__builtin_ia32_vec_set_v4di: {
unsigned NumElts = cast<cir::VectorType>(Ops[0].getType()).getSize();
uint64_t index =
Ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue();
index &= NumElts - 1;
auto indexAttr = cir::IntAttr::get(
cir::IntType::get(&getMLIRContext(), 64, false), index);
auto indexVal =
cir::ConstantOp::create(builder, getLoc(E->getExprLoc()), indexAttr);
// These builtins exist so we can ensure the index is an ICE and in range.
// Otherwise we could just do this in the header file.
return cir::VecInsertOp::create(builder, getLoc(E->getExprLoc()), Ops[0],
Ops[1], indexVal);
}
case X86::BI_mm_setcsr:
case X86::BI__builtin_ia32_ldmxcsr: {
Address tmp =
CreateMemTempWithName(E->getArg(0)->getType(), getLoc(E->getExprLoc()));
builder.createStore(getLoc(E->getExprLoc()), Ops[0], tmp);
return cir::LLVMIntrinsicCallOp::create(
builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse.ldmxcsr"), builder.getVoidTy(),
tmp.getPointer())
.getResult();
}
case X86::BI_mm_getcsr:
case X86::BI__builtin_ia32_stmxcsr: {
Address tmp = CreateMemTempWithName(E->getType(), getLoc(E->getExprLoc()));
cir::LLVMIntrinsicCallOp::create(builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.sse.stmxcsr"),
builder.getVoidTy(), tmp.getPointer())
.getResult();
return builder.createLoad(getLoc(E->getExprLoc()), tmp);
}
case X86::BI__builtin_ia32_xsave:
case X86::BI__builtin_ia32_xsave64:
case X86::BI__builtin_ia32_xrstor:
case X86::BI__builtin_ia32_xrstor64:
case X86::BI__builtin_ia32_xsaveopt:
case X86::BI__builtin_ia32_xsaveopt64:
case X86::BI__builtin_ia32_xrstors:
case X86::BI__builtin_ia32_xrstors64:
case X86::BI__builtin_ia32_xsavec:
case X86::BI__builtin_ia32_xsavec64:
case X86::BI__builtin_ia32_xsaves:
case X86::BI__builtin_ia32_xsaves64:
case X86::BI__builtin_ia32_xsetbv:
case X86::BI_xsetbv: {
std::string intrinsicName;
// TODO(cir): Refactor this once we have the proper
// infrastructure that handles `getIntrinsic` similar to OG CodeGen.
switch (BuiltinID) {
default:
llvm_unreachable("Unsupported intrinsic!");
case X86::BI__builtin_ia32_xsave:
intrinsicName = "x86.xsave";
break;
case X86::BI__builtin_ia32_xsave64:
intrinsicName = "x86.xsave64";
break;
case X86::BI__builtin_ia32_xrstor:
intrinsicName = "x86.xrstor";
break;
case X86::BI__builtin_ia32_xrstor64:
intrinsicName = "x86.xrstor64";
break;
case X86::BI__builtin_ia32_xsaveopt:
intrinsicName = "x86.xsaveopt";
break;
case X86::BI__builtin_ia32_xsaveopt64:
intrinsicName = "x86.xsaveopt64";
break;
case X86::BI__builtin_ia32_xrstors:
intrinsicName = "x86.xrstors";
break;
case X86::BI__builtin_ia32_xrstors64:
intrinsicName = "x86.xrstors64";
break;
case X86::BI__builtin_ia32_xsavec:
intrinsicName = "x86.xsavec";
break;
case X86::BI__builtin_ia32_xsavec64:
intrinsicName = "x86.xsavec64";
break;
case X86::BI__builtin_ia32_xsaves:
intrinsicName = "x86.xsaves";
break;
case X86::BI__builtin_ia32_xsaves64:
intrinsicName = "x86.xsaves64";
break;
case X86::BI__builtin_ia32_xsetbv:
case X86::BI_xsetbv:
intrinsicName = "x86.xsetbv";
break;
}
auto loc = getLoc(E->getExprLoc());
mlir::Value mhi = builder.createShift(Ops[1], 32, false);
mhi = builder.createIntCast(mhi, builder.getSInt32Ty());
mlir::Value mlo = builder.createIntCast(Ops[1], builder.getSInt32Ty());
Ops[1] = mhi;
Ops.push_back(mlo);
return cir::LLVMIntrinsicCallOp::create(
builder, loc, builder.getStringAttr(intrinsicName),
builder.getVoidTy(), Ops)
.getResult();
}
case X86::BI__builtin_ia32_xgetbv:
case X86::BI_xgetbv:
return cir::LLVMIntrinsicCallOp::create(builder, getLoc(E->getExprLoc()),
builder.getStringAttr("x86.xgetbv"),
builder.getUInt64Ty(), Ops)
.getResult();
case X86::BI__builtin_ia32_storedqudi128_mask:
case X86::BI__builtin_ia32_storedqusi128_mask:
case X86::BI__builtin_ia32_storedquhi128_mask:
case X86::BI__builtin_ia32_storedquqi128_mask:
case X86::BI__builtin_ia32_storeupd128_mask:
case X86::BI__builtin_ia32_storeups128_mask:
case X86::BI__builtin_ia32_storedqudi256_mask:
case X86::BI__builtin_ia32_storedqusi256_mask:
case X86::BI__builtin_ia32_storedquhi256_mask:
case X86::BI__builtin_ia32_storedquqi256_mask:
case X86::BI__builtin_ia32_storeupd256_mask:
case X86::BI__builtin_ia32_storeups256_mask:
case X86::BI__builtin_ia32_storedqudi512_mask:
case X86::BI__builtin_ia32_storedqusi512_mask:
case X86::BI__builtin_ia32_storedquhi512_mask:
case X86::BI__builtin_ia32_storedquqi512_mask:
case X86::BI__builtin_ia32_storeupd512_mask:
case X86::BI__builtin_ia32_storeups512_mask:
return emitX86MaskedStore(*this, Ops, llvm::Align(1),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_storesbf16128_mask:
case X86::BI__builtin_ia32_storesh128_mask:
case X86::BI__builtin_ia32_storess128_mask:
case X86::BI__builtin_ia32_storesd128_mask:
return emitX86MaskedStore(*this, Ops, llvm::Align(1),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_cvtmask2b128:
case X86::BI__builtin_ia32_cvtmask2b256:
case X86::BI__builtin_ia32_cvtmask2b512:
case X86::BI__builtin_ia32_cvtmask2w128:
case X86::BI__builtin_ia32_cvtmask2w256:
case X86::BI__builtin_ia32_cvtmask2w512:
case X86::BI__builtin_ia32_cvtmask2d128:
case X86::BI__builtin_ia32_cvtmask2d256:
case X86::BI__builtin_ia32_cvtmask2d512:
case X86::BI__builtin_ia32_cvtmask2q128:
case X86::BI__builtin_ia32_cvtmask2q256:
case X86::BI__builtin_ia32_cvtmask2q512:
return emitX86SExtMask(*this, Ops[0], convertType(E->getType()),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_cvtb2mask128:
case X86::BI__builtin_ia32_cvtb2mask256:
case X86::BI__builtin_ia32_cvtb2mask512:
case X86::BI__builtin_ia32_cvtw2mask128:
case X86::BI__builtin_ia32_cvtw2mask256:
case X86::BI__builtin_ia32_cvtw2mask512:
case X86::BI__builtin_ia32_cvtd2mask128:
case X86::BI__builtin_ia32_cvtd2mask256:
case X86::BI__builtin_ia32_cvtd2mask512:
case X86::BI__builtin_ia32_cvtq2mask128:
case X86::BI__builtin_ia32_cvtq2mask256:
case X86::BI__builtin_ia32_cvtq2mask512:
return emitX86ConvertToMask(*this, Ops[0], getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_cvtdq2ps512_mask:
case X86::BI__builtin_ia32_cvtqq2ps512_mask:
case X86::BI__builtin_ia32_cvtqq2pd512_mask:
case X86::BI__builtin_ia32_vcvtw2ph512_mask:
case X86::BI__builtin_ia32_vcvtdq2ph512_mask:
case X86::BI__builtin_ia32_vcvtqq2ph512_mask:
llvm_unreachable("vcvtw2ph256_round_mask NYI");
case X86::BI__builtin_ia32_cvtudq2ps512_mask:
case X86::BI__builtin_ia32_cvtuqq2ps512_mask:
case X86::BI__builtin_ia32_cvtuqq2pd512_mask:
case X86::BI__builtin_ia32_vcvtuw2ph512_mask:
case X86::BI__builtin_ia32_vcvtudq2ph512_mask:
case X86::BI__builtin_ia32_vcvtuqq2ph512_mask:
llvm_unreachable("vcvtuw2ph256_round_mask NYI");
case X86::BI__builtin_ia32_vfmaddss3:
case X86::BI__builtin_ia32_vfmaddsd3:
case X86::BI__builtin_ia32_vfmaddsh3_mask:
case X86::BI__builtin_ia32_vfmaddss3_mask:
case X86::BI__builtin_ia32_vfmaddsd3_mask:
llvm_unreachable("vfmaddss3 NYI");
case X86::BI__builtin_ia32_vfmaddss:
case X86::BI__builtin_ia32_vfmaddsd:
llvm_unreachable("vfmaddss NYI");
case X86::BI__builtin_ia32_vfmaddsh3_maskz:
case X86::BI__builtin_ia32_vfmaddss3_maskz:
case X86::BI__builtin_ia32_vfmaddsd3_maskz:
llvm_unreachable("vfmaddsh3_maskz NYI");
case X86::BI__builtin_ia32_vfmaddsh3_mask3:
case X86::BI__builtin_ia32_vfmaddss3_mask3:
case X86::BI__builtin_ia32_vfmaddsd3_mask3:
llvm_unreachable("vfmaddsh3_mask3 NYI");
case X86::BI__builtin_ia32_vfmsubsh3_mask3:
case X86::BI__builtin_ia32_vfmsubss3_mask3:
case X86::BI__builtin_ia32_vfmsubsd3_mask3:
llvm_unreachable("vfmaddsh3_mask3 NYI");
case X86::BI__builtin_ia32_vfmaddph512_mask:
case X86::BI__builtin_ia32_vfmaddph512_maskz:
case X86::BI__builtin_ia32_vfmaddph512_mask3:
case X86::BI__builtin_ia32_vfmaddps512_mask:
case X86::BI__builtin_ia32_vfmaddps512_maskz:
case X86::BI__builtin_ia32_vfmaddps512_mask3:
case X86::BI__builtin_ia32_vfmsubps512_mask3:
case X86::BI__builtin_ia32_vfmaddpd512_mask:
case X86::BI__builtin_ia32_vfmaddpd512_maskz:
case X86::BI__builtin_ia32_vfmaddpd512_mask3:
case X86::BI__builtin_ia32_vfmsubpd512_mask3:
case X86::BI__builtin_ia32_vfmsubph512_mask3:
llvm_unreachable("vfmaddph256_round_mask3 NYI");
case X86::BI__builtin_ia32_vfmaddsubph512_mask:
case X86::BI__builtin_ia32_vfmaddsubph512_maskz:
case X86::BI__builtin_ia32_vfmaddsubph512_mask3:
case X86::BI__builtin_ia32_vfmsubaddph512_mask3:
case X86::BI__builtin_ia32_vfmaddsubps512_mask:
case X86::BI__builtin_ia32_vfmaddsubps512_maskz:
case X86::BI__builtin_ia32_vfmaddsubps512_mask3:
case X86::BI__builtin_ia32_vfmsubaddps512_mask3:
case X86::BI__builtin_ia32_vfmaddsubpd512_mask:
case X86::BI__builtin_ia32_vfmaddsubpd512_maskz:
case X86::BI__builtin_ia32_vfmaddsubpd512_mask3:
case X86::BI__builtin_ia32_vfmsubaddpd512_mask3:
llvm_unreachable("vfmaddsubph256_round_mask3 NYI");
case X86::BI__builtin_ia32_movdqa32store128_mask:
case X86::BI__builtin_ia32_movdqa64store128_mask:
case X86::BI__builtin_ia32_storeaps128_mask:
case X86::BI__builtin_ia32_storeapd128_mask:
case X86::BI__builtin_ia32_movdqa32store256_mask:
case X86::BI__builtin_ia32_movdqa64store256_mask:
case X86::BI__builtin_ia32_storeaps256_mask:
case X86::BI__builtin_ia32_storeapd256_mask:
case X86::BI__builtin_ia32_movdqa32store512_mask:
case X86::BI__builtin_ia32_movdqa64store512_mask:
case X86::BI__builtin_ia32_storeaps512_mask:
case X86::BI__builtin_ia32_storeapd512_mask:
return emitX86MaskedStore(
*this, Ops,
getContext().getTypeAlignInChars(E->getArg(1)->getType()).getAsAlign(),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_loadups128_mask:
case X86::BI__builtin_ia32_loadups256_mask:
case X86::BI__builtin_ia32_loadups512_mask:
case X86::BI__builtin_ia32_loadupd128_mask:
case X86::BI__builtin_ia32_loadupd256_mask:
case X86::BI__builtin_ia32_loadupd512_mask:
case X86::BI__builtin_ia32_loaddquqi128_mask:
case X86::BI__builtin_ia32_loaddquqi256_mask:
case X86::BI__builtin_ia32_loaddquqi512_mask:
case X86::BI__builtin_ia32_loaddquhi128_mask:
case X86::BI__builtin_ia32_loaddquhi256_mask:
case X86::BI__builtin_ia32_loaddquhi512_mask:
case X86::BI__builtin_ia32_loaddqusi128_mask:
case X86::BI__builtin_ia32_loaddqusi256_mask:
case X86::BI__builtin_ia32_loaddqusi512_mask:
case X86::BI__builtin_ia32_loaddqudi128_mask:
case X86::BI__builtin_ia32_loaddqudi256_mask:
case X86::BI__builtin_ia32_loaddqudi512_mask:
return emitX86MaskedLoad(*this, Ops, llvm::Align(1),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_loadsbf16128_mask:
case X86::BI__builtin_ia32_loadsh128_mask:
case X86::BI__builtin_ia32_loadss128_mask:
case X86::BI__builtin_ia32_loadsd128_mask:
return emitX86MaskedLoad(*this, Ops, llvm::Align(1),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_loadaps128_mask:
case X86::BI__builtin_ia32_loadaps256_mask:
case X86::BI__builtin_ia32_loadaps512_mask:
case X86::BI__builtin_ia32_loadapd128_mask:
case X86::BI__builtin_ia32_loadapd256_mask:
case X86::BI__builtin_ia32_loadapd512_mask:
case X86::BI__builtin_ia32_movdqa32load128_mask:
case X86::BI__builtin_ia32_movdqa32load256_mask:
case X86::BI__builtin_ia32_movdqa32load512_mask:
case X86::BI__builtin_ia32_movdqa64load128_mask:
case X86::BI__builtin_ia32_movdqa64load256_mask:
case X86::BI__builtin_ia32_movdqa64load512_mask:
return emitX86MaskedLoad(
*this, Ops,
getContext().getTypeAlignInChars(E->getArg(1)->getType()).getAsAlign(),
getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_expandloaddf128_mask:
case X86::BI__builtin_ia32_expandloaddf256_mask:
case X86::BI__builtin_ia32_expandloaddf512_mask:
case X86::BI__builtin_ia32_expandloadsf128_mask:
case X86::BI__builtin_ia32_expandloadsf256_mask:
case X86::BI__builtin_ia32_expandloadsf512_mask:
case X86::BI__builtin_ia32_expandloaddi128_mask:
case X86::BI__builtin_ia32_expandloaddi256_mask:
case X86::BI__builtin_ia32_expandloaddi512_mask:
case X86::BI__builtin_ia32_expandloadsi128_mask:
case X86::BI__builtin_ia32_expandloadsi256_mask:
case X86::BI__builtin_ia32_expandloadsi512_mask:
case X86::BI__builtin_ia32_expandloadhi128_mask:
case X86::BI__builtin_ia32_expandloadhi256_mask:
case X86::BI__builtin_ia32_expandloadhi512_mask:
case X86::BI__builtin_ia32_expandloadqi128_mask:
case X86::BI__builtin_ia32_expandloadqi256_mask:
case X86::BI__builtin_ia32_expandloadqi512_mask:
return emitX86ExpandLoad(*this, Ops, getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_compressstoredf128_mask:
case X86::BI__builtin_ia32_compressstoredf256_mask:
case X86::BI__builtin_ia32_compressstoredf512_mask:
case X86::BI__builtin_ia32_compressstoresf128_mask:
case X86::BI__builtin_ia32_compressstoresf256_mask:
case X86::BI__builtin_ia32_compressstoresf512_mask:
case X86::BI__builtin_ia32_compressstoredi128_mask:
case X86::BI__builtin_ia32_compressstoredi256_mask:
case X86::BI__builtin_ia32_compressstoredi512_mask:
case X86::BI__builtin_ia32_compressstoresi128_mask:
case X86::BI__builtin_ia32_compressstoresi256_mask:
case X86::BI__builtin_ia32_compressstoresi512_mask:
case X86::BI__builtin_ia32_compressstorehi128_mask:
case X86::BI__builtin_ia32_compressstorehi256_mask:
case X86::BI__builtin_ia32_compressstorehi512_mask:
case X86::BI__builtin_ia32_compressstoreqi128_mask:
case X86::BI__builtin_ia32_compressstoreqi256_mask:
case X86::BI__builtin_ia32_compressstoreqi512_mask:
return emitX86CompressStore(*this, Ops, getLoc(E->getExprLoc()));
case X86::BI__builtin_ia32_expanddf128_mask:
case X86::BI__builtin_ia32_expanddf256_mask:
case X86::BI__builtin_ia32_expanddf512_mask:
case X86::BI__builtin_ia32_expandsf128_mask:
case X86::BI__builtin_ia32_expandsf256_mask:
case X86::BI__builtin_ia32_expandsf512_mask:
case X86::BI__builtin_ia32_expanddi128_mask:
case X86::BI__builtin_ia32_expanddi256_mask:
case X86::BI__builtin_ia32_expanddi512_mask:
case X86::BI__builtin_ia32_expandsi128_mask:
case X86::BI__builtin_ia32_expandsi256_mask:
case X86::BI__builtin_ia32_expandsi512_mask:
case X86::BI__builtin_ia32_expandhi128_mask:
case X86::BI__builtin_ia32_expandhi256_mask:
case X86::BI__builtin_ia32_expandhi512_mask:
case X86::BI__builtin_ia32_expandqi128_mask:
case X86::BI__builtin_ia32_expandqi256_mask:
case X86::BI__builtin_ia32_expandqi512_mask:
llvm_unreachable("expand*_mask NYI");
case X86::BI__builtin_ia32_compressdf128_mask:
case X86::BI__builtin_ia32_compressdf256_mask:
case X86::BI__builtin_ia32_compressdf512_mask:
case X86::BI__builtin_ia32_compresssf128_mask:
case X86::BI__builtin_ia32_compresssf256_mask:
case X86::BI__builtin_ia32_compresssf512_mask:
case X86::BI__builtin_ia32_compressdi128_mask:
case X86::BI__builtin_ia32_compressdi256_mask:
case X86::BI__builtin_ia32_compressdi512_mask:
case X86::BI__builtin_ia32_compresssi128_mask:
case X86::BI__builtin_ia32_compresssi256_mask:
case X86::BI__builtin_ia32_compresssi512_mask:
case X86::BI__builtin_ia32_compresshi128_mask:
case X86::BI__builtin_ia32_compresshi256_mask:
case X86::BI__builtin_ia32_compresshi512_mask:
case X86::BI__builtin_ia32_compressqi128_mask:
case X86::BI__builtin_ia32_compressqi256_mask:
case X86::BI__builtin_ia32_compressqi512_mask:
llvm_unreachable("compress*_mask NYI");
case X86::BI__builtin_ia32_gather3div2df:
case X86::BI__builtin_ia32_gather3div2di:
case X86::BI__builtin_ia32_gather3div4df:
case X86::BI__builtin_ia32_gather3div4di:
case X86::BI__builtin_ia32_gather3div4sf:
case X86::BI__builtin_ia32_gather3div4si:
case X86::BI__builtin_ia32_gather3div8sf:
case X86::BI__builtin_ia32_gather3div8si:
case X86::BI__builtin_ia32_gather3siv2df:
case X86::BI__builtin_ia32_gather3siv2di:
case X86::BI__builtin_ia32_gather3siv4df:
case X86::BI__builtin_ia32_gather3siv4di:
case X86::BI__builtin_ia32_gather3siv4sf:
case X86::BI__builtin_ia32_gather3siv4si:
case X86::BI__builtin_ia32_gather3siv8sf:
case X86::BI__builtin_ia32_gather3siv8si:
case X86::BI__builtin_ia32_gathersiv8df:
case X86::BI__builtin_ia32_gathersiv16sf:
case X86::BI__builtin_ia32_gatherdiv8df:
case X86::BI__builtin_ia32_gatherdiv16sf:
case X86::BI__builtin_ia32_gathersiv8di:
case X86::BI__builtin_ia32_gathersiv16si:
case X86::BI__builtin_ia32_gatherdiv8di:
case X86::BI__builtin_ia32_gatherdiv16si: {
StringRef intrinsicName;
switch (BuiltinID) {
default:
llvm_unreachable("Unexpected builtin");
case X86::BI__builtin_ia32_gather3div2df:
intrinsicName = "x86.avx512.mask.gather3div2.df";
break;
case X86::BI__builtin_ia32_gather3div2di:
intrinsicName = "x86.avx512.mask.gather3div2.di";
break;
case X86::BI__builtin_ia32_gather3div4df:
intrinsicName = "x86.avx512.mask.gather3div4.df";
break;
case X86::BI__builtin_ia32_gather3div4di:
intrinsicName = "x86.avx512.mask.gather3div4.di";
break;
case X86::BI__builtin_ia32_gather3div4sf:
intrinsicName = "x86.avx512.mask.gather3div4.sf";
break;
case X86::BI__builtin_ia32_gather3div4si:
intrinsicName = "x86.avx512.mask.gather3div4.si";
break;
case X86::BI__builtin_ia32_gather3div8sf:
intrinsicName = "x86.avx512.mask.gather3div8.sf";
break;
case X86::BI__builtin_ia32_gather3div8si:
intrinsicName = "x86.avx512.mask.gather3div8.si";
break;
case X86::BI__builtin_ia32_gather3siv2df:
intrinsicName = "x86.avx512.mask.gather3siv2.df";
break;
case X86::BI__builtin_ia32_gather3siv2di:
intrinsicName = "x86.avx512.mask.gather3siv2.di";
break;
case X86::BI__builtin_ia32_gather3siv4df:
intrinsicName = "x86.avx512.mask.gather3siv4.df";
break;
case X86::BI__builtin_ia32_gather3siv4di:
intrinsicName = "x86.avx512.mask.gather3siv4.di";
break;
case X86::BI__builtin_ia32_gather3siv4sf:
intrinsicName = "x86.avx512.mask.gather3siv4.sf";
break;
case X86::BI__builtin_ia32_gather3siv4si:
intrinsicName = "x86.avx512.mask.gather3siv4.si";
break;