|
| 1 | +//====- LoweringPrepareArm64CXXABI.cpp - Arm64 ABI specific code -----====// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, |
| 4 | +// under the Apache License v2.0 with LLVM Exceptions. |
| 5 | +// See https://llvm.org/LICENSE.txt for license information. |
| 6 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 7 | +// |
| 8 | +//===------------------------------------------------------------------===// |
| 9 | +// |
| 10 | +// This file provides ARM64 C++ ABI specific code that is used during LLVMIR |
| 11 | +// lowering prepare. |
| 12 | +// |
| 13 | +//===------------------------------------------------------------------===// |
| 14 | + |
| 15 | +#include "../IR/MissingFeatures.h" |
| 16 | +#include "../../CodeGen/TargetInfo.h" |
| 17 | +#include "LoweringPrepareItaniumCXXABI.h" |
| 18 | + |
| 19 | +#include <assert.h> |
| 20 | + |
| 21 | +using cir::LoweringPrepareCXXABI; |
| 22 | +using cir::MissingFeatures; |
| 23 | +using cir::AArch64ABIKind; |
| 24 | + |
| 25 | +using namespace mlir; |
| 26 | +using namespace mlir::cir; |
| 27 | + |
| 28 | +namespace { |
| 29 | +class LoweringPrepareAArch64CXXABI : public LoweringPrepareItaniumCXXABI { |
| 30 | +public: |
| 31 | + LoweringPrepareAArch64CXXABI(AArch64ABIKind k) : Kind(k) {} |
| 32 | + mlir::Value lowerVAArg(CIRBaseBuilderTy &builder, |
| 33 | + mlir::cir::VAArgOp op) override; |
| 34 | + |
| 35 | +private: |
| 36 | + AArch64ABIKind Kind; |
| 37 | + mlir::Value lowerAAPCSVAArg(CIRBaseBuilderTy &builder, mlir::cir::VAArgOp op); |
| 38 | +}; |
| 39 | +} // namespace |
| 40 | + |
| 41 | +LoweringPrepareCXXABI * |
| 42 | +LoweringPrepareCXXABI::createAArch64ABI(AArch64ABIKind k) { |
| 43 | + return new LoweringPrepareAArch64CXXABI(k); |
| 44 | +} |
| 45 | + |
| 46 | +mlir::Value |
| 47 | +LoweringPrepareAArch64CXXABI::lowerAAPCSVAArg(CIRBaseBuilderTy &builder, |
| 48 | + mlir::cir::VAArgOp op) { |
| 49 | + auto loc = op->getLoc(); |
| 50 | + auto valist = op->getOperand(0); |
| 51 | + auto opResTy = op.getType(); |
| 52 | + // front end should not produce non-scalar type of VAArgOp |
| 53 | + bool isSupportedType = |
| 54 | + opResTy.isa<mlir::cir::IntType, mlir::cir::SingleType, |
| 55 | + mlir::cir::PointerType, mlir::cir::BoolType, |
| 56 | + mlir::cir::DoubleType>(); |
| 57 | + |
| 58 | + // Homogenous Aggregate type not supported and indirect arg |
| 59 | + // passing not supported yet. And for these supported types, |
| 60 | + // we should not have alignment greater than 8 problem. |
| 61 | + assert(isSupportedType); |
| 62 | + assert(!MissingFeatures::handleAArch64Indirect()); |
| 63 | + |
| 64 | + bool isFloatingType = |
| 65 | + opResTy.isa<mlir::cir::SingleType, mlir::cir::DoubleType>(); |
| 66 | + |
| 67 | + // The AArch64 va_list type and handling is specified in the Procedure Call |
| 68 | + // Standard, section B.4: |
| 69 | + // |
| 70 | + // struct { |
| 71 | + // void *__stack; |
| 72 | + // void *__gr_top; |
| 73 | + // void *__vr_top; |
| 74 | + // int __gr_offs; |
| 75 | + // int __vr_offs; |
| 76 | + // }; |
| 77 | + auto curInsertionP = builder.saveInsertionPoint(); |
| 78 | + auto currentBlock = builder.getInsertionBlock(); |
| 79 | + auto boolTy = builder.getBoolTy(); |
| 80 | + |
| 81 | + auto maybeRegBlock = builder.createBlock(builder.getBlock()->getParent()); |
| 82 | + auto inRegBlock = builder.createBlock(builder.getBlock()->getParent()); |
| 83 | + auto onStackBlock = builder.createBlock(builder.getBlock()->getParent()); |
| 84 | + |
| 85 | + //======================================= |
| 86 | + // Find out where argument was passed |
| 87 | + //======================================= |
| 88 | + |
| 89 | + // If v/gr_offs >= 0 we're already using the stack for this type of |
| 90 | + // argument. We don't want to keep updating reg_offs (in case it overflows, |
| 91 | + // though anyone passing 2GB of arguments, each at most 16 bytes, deserves |
| 92 | + // whatever they get). |
| 93 | + builder.restoreInsertionPoint(curInsertionP); |
| 94 | + // 3 is the field number of __gr_offs, 4 is the field number of __vr_offs |
| 95 | + auto offsP = builder.createGetMemberOp(loc, valist, |
| 96 | + isFloatingType ? "vr_offs" : "gr_offs", |
| 97 | + isFloatingType ? 4 : 3); |
| 98 | + auto offs = builder.create<mlir::cir::LoadOp>(loc, offsP); |
| 99 | + auto zeroValue = builder.create<mlir::cir::ConstantOp>( |
| 100 | + loc, offs.getType(), mlir::cir::IntAttr::get(offs.getType(), 0)); |
| 101 | + auto cmpRes = builder.create<mlir::cir::CmpOp>(loc, boolTy, CmpOpKind::ge, |
| 102 | + offs, zeroValue); |
| 103 | + builder.create<mlir::cir::BrCondOp>(loc, cmpRes, onStackBlock, maybeRegBlock); |
| 104 | + auto newEndBlock = currentBlock->splitBlock(op); |
| 105 | + |
| 106 | + // maybeRegBlock updates the gr_offs/vr_offs pointer for next call to va_arg |
| 107 | + // on this va_list. The fact that this is done unconditionally reflects the |
| 108 | + // fact that allocating an argument to the stack also uses up all the |
| 109 | + // remaining registers of the appropriate kind. |
| 110 | + builder.setInsertionPointToEnd(maybeRegBlock); |
| 111 | + auto boundaryValue = builder.create<mlir::cir::ConstantOp>( |
| 112 | + loc, offs.getType(), |
| 113 | + mlir::cir::IntAttr::get(offs.getType(), isFloatingType ? 16 : 8)); |
| 114 | + auto newRegsOffs = builder.create<mlir::cir::BinOp>( |
| 115 | + loc, offs.getType(), mlir::cir::BinOpKind::Add, offs, boundaryValue); |
| 116 | + builder.createStore(loc, newRegsOffs, offsP); |
| 117 | + // Now we're in a position to decide whether this argument really was in |
| 118 | + // registers or not. |
| 119 | + auto maybeRegCmpRes = builder.create<mlir::cir::CmpOp>( |
| 120 | + loc, boolTy, CmpOpKind::le, newRegsOffs, zeroValue); |
| 121 | + builder.create<mlir::cir::BrCondOp>(loc, maybeRegCmpRes, inRegBlock, |
| 122 | + onStackBlock); |
| 123 | + |
| 124 | + //======================================= |
| 125 | + // Argument was on the stack |
| 126 | + //======================================= |
| 127 | + builder.setInsertionPointToEnd(onStackBlock); |
| 128 | + auto stackP = builder.createGetMemberOp(loc, valist, "stack", 0); |
| 129 | + // On big-endian platforms, the value will be right-aligned in its stack slot. |
| 130 | + assert(!MissingFeatures::handleBigEndian()); |
| 131 | + auto stack = builder.create<mlir::cir::LoadOp>(loc, stackP); |
| 132 | + auto ptrDiffTy = |
| 133 | + mlir::cir::IntType::get(builder.getContext(), 64, /*signed=*/false); |
| 134 | + auto eight = builder.create<mlir::cir::ConstantOp>( |
| 135 | + loc, ptrDiffTy, mlir::cir::IntAttr::get(ptrDiffTy, 8)); |
| 136 | + auto i8Ty = IntegerType::get(builder.getContext(), 8); |
| 137 | + auto i8PtrTy = PointerType::get(builder.getContext(), i8Ty); |
| 138 | + auto castStack = builder.createBitcast(stack, i8PtrTy); |
| 139 | + // Write the new value of __stack for the next call to va_arg |
| 140 | + auto newStackAsi8Ptr = builder.create<mlir::cir::PtrStrideOp>( |
| 141 | + loc, castStack.getType(), castStack, eight); |
| 142 | + auto newStack = builder.createBitcast(newStackAsi8Ptr, stack.getType()); |
| 143 | + builder.createStore(loc, newStack, stackP); |
| 144 | + builder.create<mlir::cir::BrOp>(loc, mlir::ValueRange{stack}, newEndBlock); |
| 145 | + |
| 146 | + //======================================= |
| 147 | + // Argument was in registers |
| 148 | + //======================================= |
| 149 | + // Now we emit the code for if the argument was originally passed in |
| 150 | + // registers. First start the appropriate block: |
| 151 | + builder.setInsertionPointToEnd(inRegBlock); |
| 152 | + auto regTopP = builder.createGetMemberOp(loc, valist, |
| 153 | + isFloatingType ? "vr_top" : "gr_top", |
| 154 | + isFloatingType ? 2 : 1); |
| 155 | + auto regTop = builder.create<mlir::cir::LoadOp>(loc, regTopP); |
| 156 | + auto castRegTop = builder.createBitcast(regTop, i8PtrTy); |
| 157 | + // On big-endian platforms, the value will be right-aligned in its stack slot. |
| 158 | + assert(!MissingFeatures::handleBigEndian()); |
| 159 | + auto resAsInt8P = builder.create<mlir::cir::PtrStrideOp>( |
| 160 | + loc, castRegTop.getType(), castRegTop, offs); |
| 161 | + auto resAsVoidP = builder.createBitcast(resAsInt8P, regTop.getType()); |
| 162 | + builder.create<mlir::cir::BrOp>(loc, mlir::ValueRange{resAsVoidP}, |
| 163 | + newEndBlock); |
| 164 | + |
| 165 | + // generate additional instructions for end block |
| 166 | + builder.setInsertionPoint(op); |
| 167 | + newEndBlock->addArgument(stack.getType(), loc); |
| 168 | + auto resP = newEndBlock->getArgument(0); |
| 169 | + assert(resP.getType().isa<mlir::cir::PointerType>()); |
| 170 | + auto opResPTy = PointerType::get(builder.getContext(), opResTy); |
| 171 | + auto castResP = builder.createBitcast(resP, opResPTy); |
| 172 | + auto res = builder.create<mlir::cir::LoadOp>(loc, castResP); |
| 173 | + return res.getResult(); |
| 174 | +} |
| 175 | + |
| 176 | +mlir::Value LoweringPrepareAArch64CXXABI::lowerVAArg(CIRBaseBuilderTy &builder, |
| 177 | + mlir::cir::VAArgOp op) { |
| 178 | + |
| 179 | + if (Kind == AArch64ABIKind::AAPCS) { |
| 180 | + return lowerAAPCSVAArg(builder, op); |
| 181 | + } |
| 182 | + assert(0 && "unsupported AArch64 CXX ABI"); |
| 183 | +} |
0 commit comments