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[Vulkan] Implement initial support for sparse resources
This commit introduces the ability to create and test sparse resources in the Vulkan backend. Key changes: - **Vulkan Backend**: Updated the Vulkan implementation to support sparse binding and residency for buffers. - **Test Infrastructure**: Enhanced test/lit.cfg.py to automatically detect and expose all boolean Vulkan features from api-query as lit features. This enables tests to use REQUIRE for specific hardware capabilities like sparseBinding and sparseResidencyBuffer. - **New Tests**: Added a suite of feature tests in test/Feature/Sparse/ to verify sparse resource behavior across different buffer types, including residency checks and partially mapped resource loads. This provides the necessary framework to validate sparse resource handling and residency behavior in HLSL-to-Vulkan pipelines.
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8 files changed

+698
-41
lines changed

8 files changed

+698
-41
lines changed

‎lib/API/VK/Device.cpp‎

Lines changed: 237 additions & 41 deletions
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‎test/Feature/Sparse/SparseByteAddressBuffer.test‎

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#--- source.hlsl
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RWByteAddressBuffer X : register(u0);
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RWStructuredBuffer<int> Out : register(u1);
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[numthreads(1,1,1)]
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void main() {
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// Index 0: Offset 0.
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Out[0] = X.Load(0);
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// Offset 128000: Second tile.
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Out[1] = X.Load(128000);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: X
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Format: Int32
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Stride: 4
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FillSize: 131072
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FillValue: 9001
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- Name: Out
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Format: Int32
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Stride: 4
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FillSize: 8
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FillValue: 0
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- Name: ExpectedOut
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Format: Int32
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Stride: 4
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Data: [9001, 0]
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Results:
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- Result: Test
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Rule: BufferExact
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Actual: Out
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Expected: ExpectedOut
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DescriptorSets:
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- Resources:
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- Name: X
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Kind: RWByteAddressBuffer
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IsReserved: true
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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TilesMapped: 1
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: !Vulkan || sparseBinding
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# REQUIRES: !Vulkan || sparseResidencyBuffer
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# XFAIL: Clang
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
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# CHECK: - Name: Out
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# CHECK-NEXT: Format: Int32
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# CHECK-NEXT: Stride: 4
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# CHECK-NEXT: Data: [ 9001, 0 ]

‎test/Feature/Sparse/SparseRWStructuredBuffer.test‎

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#--- source.hlsl
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RWStructuredBuffer<int> X : register(u0);
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RWStructuredBuffer<int> Out : register(u1);
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[numthreads(1,1,1)]
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void main() {
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// Index 0: Guaranteed to be in the first mapped tile.
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Out[0] = X[0];
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// Index 32000: 32000 * 4 bytes = 128,000 bytes.
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// If tile size is 64KB (65536 bytes), this is in the second tile (offset 65536+).
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// This should return 0 because it is unmapped.
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Out[1] = X[32000];
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: X
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Format: Int32
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Stride: 4
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FillSize: 131072 # 128KB total bytes (32768 elements)
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FillValue: 9001
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- Name: Out
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Format: Int32
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Stride: 4
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FillSize: 8
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FillValue: 0
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- Name: ExpectedOut
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Format: Int32
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Stride: 4
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Data: [9001, 0]
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Results:
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- Result: Test
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Rule: BufferExact
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Actual: Out
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Expected: ExpectedOut
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DescriptorSets:
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- Resources:
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- Name: X
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Kind: RWStructuredBuffer
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IsReserved: true
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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TilesMapped: 1
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: !Vulkan || sparseBinding
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# REQUIRES: !Vulkan || sparseResidencyBuffer
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# REQUIRES: !Vulkan || residencyNonResidentStrict
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
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# CHECK: - Name: Out
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# CHECK-NEXT: Format: Int32
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# CHECK-NEXT: Stride: 4
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# CHECK-NEXT: Data: [ 9001, 0 ]

‎test/Feature/Sparse/SparseStructuredBuffer.test‎

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#--- source.hlsl
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RWBuffer<int> X : register(u0);
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RWStructuredBuffer<int> Out : register(u1);
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[numthreads(1,1,1)]
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void main() {
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// Index 0: Guaranteed to be in the first mapped tile.
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Out[0] = X[0];
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// Index 32000: 32000 * 4 bytes = 128,000 bytes.
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// If tile size is 64KB (65536 bytes), this is in the second tile (offset 65536+).
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// This should return 0 since it is unmapped.
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Out[1] = X[32000];
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: X
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Format: Int32
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Stride: 4
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FillSize: 131072 # 128KB total bytes (32768 elements)
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FillValue: 9001
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- Name: Out
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Format: Int32
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Stride: 4
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FillSize: 8
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FillValue: 0
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- Name: ExpectedOut
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Format: Int32
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Stride: 4
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Data: [9001, 0]
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Results:
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- Result: Test
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Rule: BufferExact
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Actual: Out
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Expected: ExpectedOut
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DescriptorSets:
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- Resources:
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- Name: X
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Kind: RWBuffer
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IsReserved: true
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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TilesMapped: 1
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: !Vulkan || sparseBinding
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# REQUIRES: !Vulkan || sparseResidencyBuffer
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# REQUIRES: !Vulkan || residencyNonResidentStrict
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
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# CHECK: - Name: Out
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# CHECK-NEXT: Format: Int32
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# CHECK-NEXT: Stride: 4
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# CHECK-NEXT: Data: [ 9001, 0 ]

‎test/Feature/Sparse/SparseTypedLoad.test‎

Lines changed: 67 additions & 0 deletions
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#--- source.hlsl
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Buffer<int4> X : register(t0);
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RWStructuredBuffer<int> Out : register(u1);
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[numthreads(1,1,1)]
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void main() {
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int4 Result;
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// Index 0: Tile 0 of X. Mapped.
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Result = X.Load(0);
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Out[0] = Result.x;
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// Index 5000: Tile 1 of X. Unmapped.
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Result = X.Load(5000);
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Out[1] = Result.x;
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: X
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Format: Int32
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Channels: 4
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FillSize: 131072 # 128KB
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FillValue: 9001
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- Name: Out
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Format: Int32
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Stride: 4
35+
FillSize: 8
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DescriptorSets:
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- Resources:
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- Name: X
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Kind: Buffer
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IsReserved: true
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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TilesMapped: 1
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: !Vulkan || sparseBinding
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# REQUIRES: !Vulkan || sparseResidencyBuffer
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# REQUIRES: !Vulkan || residencyNonResidentStrict
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
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# CHECK: - Name: Out
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# CHECK-NEXT: Format: Int32
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# CHECK-NEXT: Stride: 4
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# CHECK-NEXT: Data: [ 9001, 0 ]

‎test/Feature/Sparse/SparseTypedLoadMapped.test‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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#--- source.hlsl
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Buffer<int4> X : register(t0);
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RWStructuredBuffer<int> Out : register(u1);
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[numthreads(1,1,1)]
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void main() {
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// Index 0: Tile 0. Mapped.
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Out[0] = X.Load(0).x;
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// Index 5000: Tile 1 (offset 80000). Mapped (TilesMapped: 2 = 128KB).
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Out[1] = X.Load(5000).x;
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
20+
Buffers:
21+
- Name: X
22+
Format: Int32
23+
Channels: 4
24+
FillSize: 131072
25+
FillValue: 9001
26+
- Name: Out
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Format: Int32
28+
Stride: 4
29+
FillSize: 8
30+
DescriptorSets:
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- Resources:
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- Name: X
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Kind: Buffer
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IsReserved: true
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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TilesMapped: 2
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: !Vulkan || sparseBinding
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# REQUIRES: !Vulkan || sparseResidencyBuffer
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s
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# CHECK: - Name: Out
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# CHECK-NEXT: Format: Int32
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# CHECK-NEXT: Stride: 4
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# CHECK-NEXT: Data: [ 9001, 9001 ]

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