Question about PCLK edge configuration in ESP32-S3 RGB bus

[rukihena]

Hi, thank you for this great library.

I was reading the following code in Bus_RGB.cpp:

https://github.com/lovyan03/LovyanGFX/blob/1.2.19/src/lgfx/v1/platforms/esp32s3/Bus_RGB.cpp#L260

Currently, it is implemented as:

lcd_clock.lcd_ck_idle_edge = false;
lcd_clock.lcd_ck_out_edge  = _cfg.pclk_idle_high;

From my understanding of the LCD clock configuration, it seems that the following might be more appropriate:

lcd_clock.lcd_ck_idle_edge = _cfg.pclk_idle_high;
lcd_clock.lcd_ck_out_edge  = _cfg.pclk_active_neg;

Could you please let me know if my understanding is correct, or if there is a specific reason for the current implementation?

Thank you in advance.

[tobozo]

Hi,

Bus_Parallel8 and Bus_Parallel16 also have this setting hardcoded (but with a different value) so it's probably intentional.

Did you encounter a situation where changing that value was relevant?

[rukihena]

I noticed this issue while testing a CYD board called ESP32-8048S050C.

The board definition I am using is the following:
https://github.com/rzeldent/platformio-espressif32-sunton/blob/main/esp32-8048S050C.json#L41

With the configuration below, the display mostly works, but fine details are not rendered correctly (for example, small text or thin lines appear corrupted):

cfg.pclk_active_neg = ST7262_PANEL_CONFIG_TIMINGS_FLAGS_PCLK_ACTIVE_NEG; // true
cfg.de_idle_high    = ST7262_PANEL_CONFIG_TIMINGS_FLAGS_DE_IDLE_HIGH;    // false

If I change the configuration to the following, the display works reasonably well for now:

cfg.pclk_active_neg = false; // (effectively unused)
cfg.de_idle_high    = true;

Based on the meaning of these configuration variables, I would expect the display to work correctly with the first configuration, and I am trying to understand why the alternative settings are required in this case.

I also understand that modifying the library could affect existing users, so I am not suggesting a change lightly.