[simple_system] Instruction cycle delay parameter

Add a parameter to Simple system to delay the instruction requests and
expose this in the FuseSoC build instruction.

Author: marnovandermaas

examples/simple_system/ibex_simple_system.core

@@ -43,6 +43,12 @@ parameters:
     paramtype: vlogdefine
     description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
 
+  InstrCycleDelay:
+    datatype: str
+    default: ibex_pkg::RegFileFF
+    paramtype: vlogdefine
+    description: "Number of cycles to delay the instruction RAM access. This is on top of the single-cycle access that the RAM requires."
+
   ICache:
     datatype: int
     default: 0
@@ -137,6 +143,7 @@ targets:
       - RV32B
       - RV32ZC
       - RegFile
+      - InstrCycleDelay
       - ICache
       - ICacheScramble
       - ICacheECC

examples/simple_system/rtl/ibex_simple_system.sv

@@ -22,6 +22,10 @@
   `define RegFile ibex_pkg::RegFileFF
 `endif
 
+`ifndef InstrCycleDelay
+  `define InstrCycleDelay 0
+`endif
+
 /**
  * Ibex simple system
  *
@@ -274,6 +278,7 @@ module ibex_simple_system (
   // SRAM block for instruction and data storage
   ram_2p #(
       .Depth(1024*1024/4),
+      .BExtraDelay(`InstrCycleDelay),
       .MemInitFile(SRAMInitFile)
     ) u_ram (
       .clk_i       (clk_sys),

examples/sw/benchmarks/README.md

@@ -1,6 +1,6 @@
 # Benchmarks
 
-This directory contains benchmarks that can be run on ibex simple system.
+This directory contains benchmarks that can be run on Ibex simple system.
 Benchmarks may rely on code external to this directory (e.g. it may be found in
 `vendor/`) see the specific benchmark information below for details on how to
 build and run each benchmark and where benchmark code is located.
@@ -10,14 +10,21 @@ build and run each benchmark and where benchmark code is located.
 All of these benchmarks run on Simple System. A verilator simulation suitable
 for running them can be built with:
 
-```
+```shell
 fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system `./util/ibex_config.py maxperf fusesoc_opts`
 ```
 
 This will build a simulation of Ibex in the 'maxperf' configuration.
 It is one of several pre-defined ibex configurations, others can be used.
 These are specified in the `ibex_configs.yaml` file.
 
+You can also test how the instruction cache affects performance.
+To see this effect you must specify a delay on the instruction accesses becaus with single-cycle RAM access an isntruction cache does not help.
+
+```shell
+fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system `./util/ibex_config.py maxperf-pmp-bmfull-icache fusesoc_opts` --InstrCycleDelay=5
+```
+
 See examples/simple_system/README.md for full details.
 
 ## CoreMark
@@ -32,13 +39,13 @@ running on simple system is found in `examples/sw/benchmarks/coremark`.
 
 To build CoreMark:
 
-```
+```shell
 make -C ./examples/sw/benchmarks/coremark/
 ```
 
 To run CoreMark (after building a suitable simulator binary, see above):
 
-```
+```shell
 build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
 ```
 
@@ -71,7 +78,7 @@ Correct operation validated. See README.md for run and reporting rules.
 Different ISAs (to choose different RISC-V ISA extensions) can be selected by
 passing the desired ISA string into `RV_ISA` when invoking make.
 
-```
+```shell
 make -C ./examples/sw/benchmarks/coremark clean
 make -C ./examples/sw/benchmarks/coremark RV_ISA=rv32imc
 ```