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thommythomasoSamuelRiedel
thommythomaso
authored and
SamuelRiedel
committed
[rtl] Generalize SRAM configuration interfaces
1 parent 022f084 commit c6edaa4

32 files changed

Lines changed: 622 additions & 109 deletions

‎doc/02_user/integration.rst‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,10 @@ Instantiation Template
118118
.rst_ni (),
119119
.test_en_i (),
120120
.scan_rst_ni (),
121-
.ram_cfg_i (),
121+
.ram_cfg_icache_tag_i (),
122+
.ram_cfg_icache_tag_o (),
123+
.ram_cfg_icache_data_i (),
124+
.ram_cfg_icache_data_o (),
122125
123126
// Configuration
124127
.hart_id_i (),
@@ -284,8 +287,17 @@ Interfaces
284287
| ``scan_rst_ni`` | 1 | in | Test controlled reset. If DFT not |
285288
| | | | used, tie off to 1. |
286289
+----------------------------+-------------------------+-----+----------------------------------------+
287-
| ``ram_cfg_i`` | 10 | in | RAM configuration inputs, routed to |
288-
| | | | the icache RAMs |
290+
| ``ram_cfg_icache_tag_i`` | ram_1p_cfg_req_t | in | Per-way icache tag RAM config input, |
291+
| | | | routed to the icache tag RAMs |
292+
+----------------------------+-------------------------+-----+----------------------------------------+
293+
| ``ram_cfg_icache_tag_o`` | ram_1p_cfg_rsp_t | out | Per-way icache tag RAM config |
294+
| | | | response from the icache tag RAMs |
295+
+----------------------------+-------------------------+-----+----------------------------------------+
296+
| ``ram_cfg_icache_data_i`` | ram_1p_cfg_req_t | in | Per-way icache data RAM config input, |
297+
| | | | routed to the icache data RAMs |
298+
+----------------------------+-------------------------+-----+----------------------------------------+
299+
| ``ram_cfg_icache_data_o`` | ram_1p_cfg_rsp_t | out | Per-way icache data RAM config |
300+
| | | | response from the icache data RAMs |
289301
+----------------------------+-------------------------+-----+----------------------------------------+
290302
| ``hart_id_i`` | 32 | in | Hart ID, usually static, can be read |
291303
| | | | from :ref:`csr-mhartid` CSR |

‎dv/formal/check/top.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,10 @@ module top import ibex_pkg::*; #(
5151
`endif
5252

5353
input logic test_en_i,
54-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i,
55-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o,
56-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i,
57-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o,
54+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_i,
55+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_o,
56+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_i,
57+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_o,
5858

5959
input logic [31:0] hart_id_i,
6060
input logic [31:0] boot_addr_i,

‎dv/riscv_compliance/rtl/ibex_riscv_compliance.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -171,10 +171,10 @@ module ibex_riscv_compliance (
171171

172172
.test_en_i ('b0 ),
173173
.scan_rst_ni (1'b1 ),
174-
.ram_cfg_icache_tag_i ('b0 ),
175-
.ram_cfg_rsp_icache_tag_o ( ),
176-
.ram_cfg_icache_data_i ('b0 ),
177-
.ram_cfg_rsp_icache_data_o ( ),
174+
.ram_cfg_icache_tag_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
175+
.ram_cfg_icache_tag_o ( ),
176+
.ram_cfg_icache_data_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
177+
.ram_cfg_icache_data_o ( ),
178178

179179
.hart_id_i (32'b0 ),
180180
// First instruction executed is at 0x0 + 0x80

‎dv/uvm/core_ibex/tb/core_ibex_tb_top.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,10 @@ module core_ibex_tb_top;
125125

126126
.test_en_i (1'b0 ),
127127
.scan_rst_ni (1'b1 ),
128-
.ram_cfg_icache_tag_i ('b0 ),
129-
.ram_cfg_rsp_icache_tag_o ( ),
130-
.ram_cfg_icache_data_i ('b0 ),
131-
.ram_cfg_rsp_icache_data_o ( ),
128+
.ram_cfg_icache_tag_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
129+
.ram_cfg_icache_tag_o ( ),
130+
.ram_cfg_icache_data_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
131+
.ram_cfg_icache_data_o ( ),
132132

133133
.hart_id_i (32'b0 ),
134134
.boot_addr_i (BootAddr ),

‎dv/uvm/icache/dv/tb/tb.sv‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,8 @@ module tb #(
160160
.rvalid_o (ram_if.ic_tag_rvalid[way]),
161161
.raddr_o (),
162162
.rerror_o (),
163-
.cfg_i ('0),
163+
.cfg_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
164+
.cfg_o (),
164165
.wr_collision_o (),
165166
.write_pending_o (),
166167
.alert_o ()
@@ -195,7 +196,8 @@ module tb #(
195196
.rvalid_o (ram_if.ic_data_rvalid[way]),
196197
.raddr_o (),
197198
.rerror_o (),
198-
.cfg_i ('0),
199+
.cfg_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
200+
.cfg_o (),
199201
.wr_collision_o (),
200202
.write_pending_o (),
201203
.alert_o ()

‎examples/simple_system/rtl/ibex_simple_system.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -231,10 +231,10 @@ module ibex_simple_system (
231231

232232
.test_en_i (1'b0),
233233
.scan_rst_ni (1'b1),
234-
.ram_cfg_icache_tag_i (prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT),
235-
.ram_cfg_rsp_icache_tag_o (),
236-
.ram_cfg_icache_data_i (prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT),
237-
.ram_cfg_rsp_icache_data_o (),
234+
.ram_cfg_icache_tag_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
235+
.ram_cfg_icache_tag_o (),
236+
.ram_cfg_icache_data_i ('{default: prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT}),
237+
.ram_cfg_icache_data_o (),
238238

239239
.hart_id_i (32'b0),
240240
// First instruction executed is at 0x0 + 0x80

‎rtl/ibex_top.sv‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -65,10 +65,10 @@ module ibex_top import ibex_pkg::*; #(
6565

6666
// enable all clock gates for testing
6767
input logic test_en_i,
68-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i,
69-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o,
70-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i,
71-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o,
68+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_i,
69+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_o,
70+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_i,
71+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_o,
7272

7373
input logic [31:0] hart_id_i,
7474
input logic [31:0] boot_addr_i,
@@ -633,8 +633,8 @@ module ibex_top import ibex_pkg::*; #(
633633
.rvalid_o (),
634634
.raddr_o (),
635635
.rerror_o (),
636-
.cfg_i (ram_cfg_icache_tag_i),
637-
.cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way]),
636+
.cfg_i (ram_cfg_icache_tag_i[way]),
637+
.cfg_o (ram_cfg_icache_tag_o[way]),
638638
.wr_collision_o (),
639639
.write_pending_o (),
640640

@@ -671,8 +671,8 @@ module ibex_top import ibex_pkg::*; #(
671671
.rvalid_o (),
672672
.raddr_o (),
673673
.rerror_o (),
674-
.cfg_i (ram_cfg_icache_data_i),
675-
.cfg_rsp_o (ram_cfg_rsp_icache_data_o[way]),
674+
.cfg_i (ram_cfg_icache_data_i[way]),
675+
.cfg_o (ram_cfg_icache_data_o[way]),
676676
.wr_collision_o (),
677677
.write_pending_o (),
678678

@@ -728,8 +728,8 @@ module ibex_top import ibex_pkg::*; #(
728728
.wmask_i ({TagSizeECC{1'b1}}),
729729

730730
.rdata_o (ic_tag_rdata[way]),
731-
.cfg_i (ram_cfg_icache_tag_i),
732-
.cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way])
731+
.cfg_i (ram_cfg_icache_tag_i[way]),
732+
.cfg_o (ram_cfg_icache_tag_o[way])
733733
);
734734

735735
// Data RAM instantiation
@@ -749,8 +749,8 @@ module ibex_top import ibex_pkg::*; #(
749749
.wmask_i ({LineSizeECC{1'b1}}),
750750

751751
.rdata_o (ic_data_rdata[way]),
752-
.cfg_i (ram_cfg_icache_data_i),
753-
.cfg_rsp_o (ram_cfg_rsp_icache_data_o[way])
752+
.cfg_i (ram_cfg_icache_data_i[way]),
753+
.cfg_o (ram_cfg_icache_data_o[way])
754754
);
755755

756756
assign icache_tag_alert = '{default:'b0};
@@ -763,12 +763,12 @@ module ibex_top import ibex_pkg::*; #(
763763
logic unused_ram_cfg;
764764
logic unused_ram_inputs;
765765

766-
assign unused_ram_cfg = |{ram_cfg_icache_tag_i, ram_cfg_icache_data_i};
767-
assign ram_cfg_rsp_icache_tag_o = '0;
768-
assign ram_cfg_rsp_icache_data_o = '0;
769-
assign unused_ram_inputs = (|ic_tag_req) & ic_tag_write & (|ic_tag_addr) & (|ic_tag_wdata) &
770-
(|ic_data_req) & ic_data_write & (|ic_data_addr) & (|ic_data_wdata) &
771-
(|NumAddrScrRounds);
766+
assign unused_ram_cfg = |{ram_cfg_icache_tag_i, ram_cfg_icache_data_i};
767+
assign ram_cfg_icache_tag_o = '{default: prim_ram_1p_pkg::RAM_1P_CFG_RSP_DEFAULT};
768+
assign ram_cfg_icache_data_o = '{default: prim_ram_1p_pkg::RAM_1P_CFG_RSP_DEFAULT};
769+
assign unused_ram_inputs = (|ic_tag_req) & ic_tag_write & (|ic_tag_addr) &
770+
(|ic_tag_wdata) & (|ic_data_req) & ic_data_write &
771+
(|ic_data_addr) & (|ic_data_wdata) & (|NumAddrScrRounds);
772772

773773
assign ic_tag_rdata = '{default:'b0};
774774
assign ic_data_rdata = '{default:'b0};

‎rtl/ibex_top_tracing.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,10 @@ module ibex_top_tracing import ibex_pkg::*; #(
4444
// enable all clock gates for testing
4545
input logic test_en_i,
4646
input logic scan_rst_ni,
47-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i,
48-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o,
49-
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i,
50-
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o,
47+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_i,
48+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_tag_o,
49+
input prim_ram_1p_pkg::ram_1p_cfg_req_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_i,
50+
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_icache_data_o,
5151

5252

5353
input logic [31:0] hart_id_i,
@@ -232,9 +232,9 @@ module ibex_top_tracing import ibex_pkg::*; #(
232232
.test_en_i,
233233
.scan_rst_ni,
234234
.ram_cfg_icache_tag_i,
235-
.ram_cfg_rsp_icache_tag_o,
235+
.ram_cfg_icache_tag_o,
236236
.ram_cfg_icache_data_i,
237-
.ram_cfg_rsp_icache_data_o,
237+
.ram_cfg_icache_data_o,
238238

239239
.hart_id_i,
240240
.boot_addr_i,

‎shared/rtl/ram_1p.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,6 @@ module ram_1p #(
6666
.wmask_i (wmask),
6767
.rdata_o (rdata_o),
6868
.cfg_i ('0),
69-
.cfg_rsp_o ()
69+
.cfg_o ()
7070
);
7171
endmodule

‎shared/rtl/ram_2p.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ module ram_2p #(
109109
.b_wmask_i (b_wmask),
110110
.b_rdata_o (b_rdata_d),
111111
.cfg_i ('0),
112-
.cfg_rsp_o ()
112+
.cfg_o ()
113113
);
114114

115115
endmodule

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