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[dv,pwm] DV improvements for PWM #3674

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[dv,pwm] DV improvements for PWM

[dv,pwm] DV improvements for PWM #3674

Triggered via pull request December 19, 2024 23:34
@alees24alees24
opened #25718
alees24:pwm-dv-work
Status Failure
Total duration 2h 20m 54s
Artifacts 31
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

ci.yml

on: pull_request
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9 errors and 1 warning
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Some target names have banned characters.
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Build and test software
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Verible lint: hw/ip/pwm/dv/env/pwm_scoreboard.sv#L483
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 117 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 117 [Style: line-length] [line-length]" location:{path:"./hw/ip/pwm/dv/env/pwm_scoreboard.sv" range:{start:{line:483 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

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