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[cov,ci] Collect test coverage on CI #18815

[cov,ci] Collect test coverage on CI

[cov,ci] Collect test coverage on CI #18815

Triggered via pull request February 11, 2026 13:01
Status Failure
Total duration 2h 7m 20s
Artifacts 25

ci.yml

on: pull_request
Earl Grey for CW310  /  Build bitstream
1m 57s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 56s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 59s
Earl Grey for CW340 / Build bitstream
OTBN Crypto Tests Coverage
27m 5s
OTBN Crypto Tests Coverage
Unit Test Coverage
13m 52s
Unit Test Coverage
CW310 Test ROM Tests Coverage  /  FPGA test
55m 6s
CW310 Test ROM Tests Coverage / FPGA test
CW310 ROM Tests Coverage  /  FPGA test
1h 32m
CW310 ROM Tests Coverage / FPGA test
CW310 ROM_EXT Tests Coverage  /  FPGA test
1h 15m
CW310 ROM_EXT Tests Coverage / FPGA test
CW310 SiVal Tests Coverage  /  FPGA test
2h 2m
CW310 SiVal Tests Coverage / FPGA test
CW310 SiVal ROM_EXT Tests Coverage  /  FPGA test
2h 0m
CW310 SiVal ROM_EXT Tests Coverage / FPGA test
CW310 Manufacturing Tests Coverage  /  FPGA test
2h 2m
CW310 Manufacturing Tests Coverage / FPGA test
Hyper310 ROM_EXT Tests Coverage  /  FPGA test
2h 0m
Hyper310 ROM_EXT Tests Coverage / FPGA test
CW340 Test ROM Tests Coverage  /  FPGA test
2m 14s
CW340 Test ROM Tests Coverage / FPGA test
CW340 ROM Tests Coverage  /  FPGA test
1m 58s
CW340 ROM Tests Coverage / FPGA test
CW340 ROM_EXT Tests Coverage  /  FPGA test
1h 1m
CW340 ROM_EXT Tests Coverage / FPGA test
CW340 SiVal Tests Coverage  /  FPGA test
42m 1s
CW340 SiVal Tests Coverage / FPGA test
CW340 SiVal ROM_EXT Tests Coverage  /  FPGA test
1h 2m
CW340 SiVal ROM_EXT Tests Coverage / FPGA test
CW340 Manufacturing Tests Coverage  /  FPGA test
2h 0m
CW340 Manufacturing Tests Coverage / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Publish Coverage Report  /  Publish Coverage Report
1m 7s
Publish Coverage Report / Publish Coverage Report
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40 errors and 22 warnings
Earl Grey for CW310 Hyperdebug / Build bitstream
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
Earl Grey for CW310 / Build bitstream
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
Earl Grey for CW340 / Build bitstream
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
Lint (quick)
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW340 ROM Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW340 Test ROM Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.ConfigBoundsTest/5: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1411
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1423 Expected equality of these values: error Which is: 256857859 param.expect Which is: 105862915
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.ConfigBoundsTest/3: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1411
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1423 Expected equality of these values: error Which is: 256857859 param.expect Which is: 105862915
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.FlashBoundsTest/9: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1370
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1374 Expected equality of these values: overlap Which is: 1849 p.overlap ? kHardenedBoolTrue : kHardenedBoolFalse Which is: 468
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.FlashBoundsTest/7: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1370
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1374 Expected equality of these values: overlap Which is: 1849 p.overlap ? kHardenedBoolTrue : kHardenedBoolFalse Which is: 468
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.FlashBoundsTest/6: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1370
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1374 Expected equality of these values: overlap Which is: 1849 p.overlap ? kHardenedBoolTrue : kHardenedBoolFalse Which is: 468
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.FlashBoundsTest/5: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1370
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1375 Expected equality of these values: exclusive Which is: 1849 p.exclusive ? kHardenedBoolTrue : kHardenedBoolFalse Which is: 468
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.FlashBoundsTest/4: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1370
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1375 Expected equality of these values: exclusive Which is: 1849 p.exclusive ? kHardenedBoolTrue : kHardenedBoolFalse Which is: 468
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.BadFlashConfig/7: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1322
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1329 Expected equality of these values: error Which is: 256857859 expected Which is: 307189507
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.BadFlashConfig/6: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1322
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1329 Expected equality of these values: error Which is: 256857859 expected Which is: 307189507
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc.BadFlashConfig/5: sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc#L1322
sw/device/silicon_creator/lib/ownership/owner_block_unittest.cc:1329 Expected equality of these values: error Which is: 256857859 expected Which is: 273635075
Unit Test Coverage
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
OTBN Crypto Tests Coverage
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW340 SiVal Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW310 Test ROM Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW340 ROM_EXT Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW340 SiVal ROM_EXT Tests Coverage / FPGA test
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
CW310 ROM_EXT Tests Coverage / FPGA test
Process completed with exit code 3.
CW310 ROM Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 1h30m0s
CW310 ROM Tests Coverage / FPGA test
The operation was canceled.
Hyper310 ROM_EXT Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 2h0m0s
Hyper310 ROM_EXT Tests Coverage / FPGA test
The operation was canceled.
CW310 SiVal ROM_EXT Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 2h0m0s
CW310 SiVal ROM_EXT Tests Coverage / FPGA test
The operation was canceled.
CW340 Manufacturing Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 2h0m0s
CW340 Manufacturing Tests Coverage / FPGA test
The operation was canceled.
CW310 SiVal Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 2h0m0s
CW310 SiVal Tests Coverage / FPGA test
The operation was canceled.
CW310 Manufacturing Tests Coverage / FPGA test
The job has exceeded the maximum execution time of 2h0m0s
CW310 Manufacturing Tests Coverage / FPGA test
The operation was canceled.
Publish Coverage Report / Publish Coverage Report
The process '/home/runner/.local/share/venv/bin/uv' failed with exit code 2
Earl Grey for CW310 Hyperdebug / Build bitstream
Failed to restore: Cache service responded with 400
Earl Grey for CW310 / Build bitstream
Failed to restore: Cache service responded with 400
Earl Grey for CW340 / Build bitstream
Failed to restore: Cache service responded with 400
Lint (quick)
Failed to restore: Cache service responded with 400
CW340 ROM Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW340 Test ROM Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
Unit Test Coverage
Failed to restore: Cache service responded with 400
Lint (slow)
Failed to save: <h2>Our services aren't available right now</h2><p>We're working to restore all services as soon as possible. Please check back soon.</p>0jYGMaQAAAAC0GweIzWEiSJr7d3M49h9JQ0hHRURHRTE5MTEARWRnZQ==
Lint (slow)
Failed to restore: Cache service responded with 400
OTBN Crypto Tests Coverage
Failed to restore: Cache service responded with 400
CW340 SiVal Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 Test ROM Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW340 ROM_EXT Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW340 SiVal ROM_EXT Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 ROM_EXT Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 ROM Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
Hyper310 ROM_EXT Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 SiVal ROM_EXT Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW340 Manufacturing Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 SiVal Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
CW310 Manufacturing Tests Coverage / FPGA test
Failed to restore: Cache service responded with 400
Publish Coverage Report / Publish Coverage Report
Failed to restore: Cache service responded with 400

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