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[rv_core_ibex, rtl] Lockstep for instruction & data bus interface #18829

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[rv_core_ibex, rtl] Lockstep for instruction & data bus interface

[rv_core_ibex, rtl] Lockstep for instruction & data bus interface #18829

Triggered via pull request February 11, 2026 16:53
@nasahlpanasahlpa
synchronize #29295
nasahlpa:rv_core_addr_translation_lockstep
Status Queued
Total duration –
Artifacts 8

ci.yml

on: pull_request
Lint (quick)
4m 52s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
1h 2m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
46m 27s
Earl Grey for CW310 Hyperdebug / Build bitstream
Lint (slow)
12m 59s
Lint (slow)
Build documentation
4m 59s
Build documentation
Airgapped build
18m 8s
Airgapped build
Verible lint
1m 11s
Verible lint
Run OTBN smoke Test
2m 39s
Run OTBN smoke Test
Run OTBN crypto tests
1m 48s
Run OTBN crypto tests
Verilated English Breakfast
5m 29s
Verilated English Breakfast
Verilated Earl Grey
1h 30m
Verilated Earl Grey
CW305's Bitstream
23m 55s
CW305's Bitstream
Build Docker Containers
2m 17s
Build Docker Containers
Build and test software
21m 35s
Build and test software
Build and test Darjeeling software
16m 49s
Build and test Darjeeling software
QEMU smoketest
2m 21s
QEMU smoketest
Test QEMU local development override
8m 56s
Test QEMU local development override
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
4s
Cache bitstreams to GCP
CW310 Test ROM Tests  /  FPGA test
23m 48s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
1h 30m
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
Merge blocker
2s
Merge blocker
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6 errors and 1 warning
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
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Lint (slow)
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Build and test software
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CW310 ROM Tests / FPGA test
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CW310 ROM Tests / FPGA test
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Verilated English Breakfast
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Artifacts

Produced during runtime
Name Size Digest
chip_englishbreakfast_cw305
1.47 MB
sha256:f5384de50251db3a8eeb7ad8725436d97dc965fe57264867d4c6dcb0894be51d
docs
83.2 MB
sha256:33d5340e8ad92d1269cf9683cadd39f60ea952b672850b176ec569b5510dc624
execute_test_rom_fpga_tests_cw310-targets
314 Bytes
sha256:7ac9d82a604eb0b1acbefaec724f3388b9374b74d673d5f3daa187f591cc5f96
execute_test_rom_fpga_tests_cw310-test-results
3.18 KB
sha256:0d55b71729c0c252822aee37f741ead341eb28240c0625311fe1fbf7f09c422b
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.84 MB
sha256:59eec302f04bf56dedd5a46c0727164298f6bbc6fab34b475ee091096118cec0
partial-build-bin-chip_earlgrey_cw340
9.82 MB
sha256:b2fcab5f348411304f56a824155cdf2c3dc1f9ca69896cd06062914e57ca1b03
sw_build_test-test-results
248 KB
sha256:efe842a61f9eb97404c8704b161a9328ac576d42ac55b9bcbc25ee3de7104670
verilator_earlgrey-test-results
9.56 KB
sha256:aa5831fcfb0389a5e3cb1abe2baaddc0a30e1938b90d3bf29592e0f0455931cc