[ci] Disable timeout filter in FPGA runner script

This will allow `long` and `eternal` tests to be run in nightlies and
also ensures that the `target_pattern_file.txt` which is uploaded as an
artifact is an accurate list of the tests being run and isn't filtered
further.

Signed-off-by: James Wainwright <[email protected]>

Author: jwnrt

ci/scripts/run-fpga-tests.sh

@@ -51,7 +51,6 @@ trap './bazelisk.sh run //sw/host/opentitantool -- --rcfile= --interface=${fpga}
     --run_under=//ci/scripts:run_test \
     --define DISABLE_VERILATOR_BUILD=true \
     --nokeep_going \
-    --test_timeout_filters=short,moderate \
     --test_output=all \
     --build_tests_only \
     --define "$fpga"=lowrisc \