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[fpga,sim_verilator] Adjust paths for new fusesoc
Adjust the paths to fusesoc FPGA outputs to accommodate the extra layer of hierarchy for --build-root. We might want to consider using --work-root to shorten these long paths in the future. Co-authored-by: Alexander Williams <[email protected]> Signed-off-by: Hugo McNally <[email protected]>
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.github/workflows/bitstream.yml

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,11 +82,21 @@ jobs:
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if: steps.strategy.outputs.bitstreamStrategy != 'cached'
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run: |
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. util/build_consts.sh
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vlnv_path=lowrisc_systems_chip_${{ parameters.top_name }}_${{ parameters.design_suffix }}_0.1
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design_name=chip_${{ parameters.top_name }}_${{ parameters.design_suffix }}
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echo "Synthesis log"
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cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/synth_1/runme.log || true
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cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/synth_1/runme.log || true
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echo "Implementation log"
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cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/impl_1/runme.log || true
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cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/runme.log || true
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echo "Utilization report"
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cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_utilization_placed.rpt || true
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echo "Timing summary report"
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cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_timing_summary_routed.rpt || true
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- name: Upload step outputs
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uses: actions/upload-artifact@v4

ci/scripts/build-chip-verilator.sh

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,15 @@ case "$tl" in
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earlgrey)
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fileset=fileset_top
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fusesoc_core=lowrisc:dv:chip_verilator_sim
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vlnv_path=lowrisc_dv_chip_verilator_sim_0.1
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vname=Vchip_sim_tb
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verilator_options="--threads 4"
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make_options="-j 4"
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;;
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englishbreakfast)
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fileset=fileset_topgen
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fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
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vlnv_path=lowrisc_systems_chip_englishbreakfast_verilator_0.1
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vname=Vchip_englishbreakfast_verilator
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# Englishbreakfast on CI runs on a 2-core CPU
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verilator_options="--threads 2"
@@ -55,5 +57,5 @@ fusesoc --cores-root=. \
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--verilator_options="${verilator_options}" \
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--make_options="${make_options}"
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cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
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cp "$OBJ_DIR/hw/${vlnv_path}/sim-verilator/${vname}" \
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"$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"

hw/BUILD

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ fusesoc_build(
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data = ["//hw/ip/otbn:all_files"],
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make_options = ":make_options",
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output_groups = {
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"binary": ["sim-verilator/Vchip_sim_tb"],
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"binary": ["lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
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},
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systems = ["lowrisc:dv:chip_verilator_sim"],
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tags = [

hw/bitstream/vivado/BUILD

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ _CW340_TESTROM_PATH = _CW310_TESTROM_PATH
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_OTP_RMA_PATH = "{}/$(location {})".format(_PREFIX, _OTP_RMA)
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_FPGA_PATH_TMPL = "lowrisc_systems_{}_0.1/synth-vivado/{}"
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# Note: all of the targets are tagged with "manual" to prevent them from being
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# matched by bazel wildcards like "//...". In order to build the bitstream,
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# you need to ask for it directly or by dependency via another rule, such as
@@ -51,10 +53,10 @@ fusesoc_build(
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"--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
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],
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output_groups = {
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"bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"],
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"rom_mmi": ["synth-vivado/rom.mmi"],
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"otp_mmi": ["synth-vivado/otp.mmi"],
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"logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.runs/"],
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"bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.bit")],
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"rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "rom.mmi")],
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"otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "otp.mmi")],
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"logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.runs/")],
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},
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systems = ["lowrisc:systems:chip_earlgrey_cw310"],
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tags = ["manual"],
@@ -101,10 +103,10 @@ fusesoc_build(
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"--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
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],
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output_groups = {
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"bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit"],
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"rom_mmi": ["synth-vivado/rom.mmi"],
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"otp_mmi": ["synth-vivado/otp.mmi"],
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"logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/"],
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"bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit")],
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"rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "rom.mmi")],
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"otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "otp.mmi")],
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"logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/")],
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},
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systems = ["lowrisc:systems:chip_earlgrey_cw310_hyperdebug"],
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tags = ["manual"],
@@ -151,10 +153,10 @@ fusesoc_build(
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"--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
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],
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output_groups = {
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"bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.bit"],
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"rom_mmi": ["synth-vivado/rom.mmi"],
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"otp_mmi": ["synth-vivado/otp.mmi"],
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"logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.runs/"],
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"bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.bit")],
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"rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "rom.mmi")],
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"otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "otp.mmi")],
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"logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.runs/")],
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},
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systems = ["lowrisc:systems:chip_earlgrey_cw340"],
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tags = ["manual"],

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