[fpga,sim_verilator] Adjust paths for new fusesoc

Adjust the paths to fusesoc FPGA outputs to accommodate the extra layer
of hierarchy for --build-root. We might want to consider using
--work-root to shorten these long paths in the future.

Co-authored-by: Alexander Williams <[email protected]>
Signed-off-by: Hugo McNally <[email protected]>

Author: HU90m

.github/workflows/bitstream.yml

@@ -82,11 +82,21 @@ jobs:
         if: steps.strategy.outputs.bitstreamStrategy != 'cached'
         run: |
           . util/build_consts.sh
+
+          vlnv_path=lowrisc_systems_chip_${{ parameters.top_name }}_${{ parameters.design_suffix }}_0.1
+          design_name=chip_${{ parameters.top_name }}_${{ parameters.design_suffix }}
+
           echo "Synthesis log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/synth_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/synth_1/runme.log || true
 
           echo "Implementation log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/impl_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/runme.log || true
+
+          echo "Utilization report"
+          cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_utilization_placed.rpt || true
+
+          echo "Timing summary report"
+          cat $OBJ_DIR/hw/top_${{ parameters.top_name }}/${design_name}/build.fpga_${{ parameters.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_timing_summary_routed.rpt || true
 
       - name: Upload step outputs
         uses: actions/upload-artifact@v4

ci/scripts/build-chip-verilator.sh

@@ -20,13 +20,15 @@ case "$tl" in
     earlgrey)
         fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
+        vlnv_path=lowrisc_dv_chip_verilator_sim_0.1
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
         fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
+        vlnv_path=lowrisc_systems_chip_englishbreakfast_verilator_0.1
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
@@ -55,5 +57,5 @@ fusesoc --cores-root=. \
   --verilator_options="${verilator_options}" \
   --make_options="${make_options}"
 
-cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
+cp "$OBJ_DIR/hw/${vlnv_path}/sim-verilator/${vname}" \
    "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"

hw/BUILD

@@ -43,7 +43,7 @@ fusesoc_build(
     data = ["//hw/ip/otbn:all_files"],
     make_options = ":make_options",
     output_groups = {
-        "binary": ["sim-verilator/Vchip_sim_tb"],
+        "binary": ["lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
     },
     systems = ["lowrisc:dv:chip_verilator_sim"],
     tags = [

hw/bitstream/vivado/BUILD

@@ -32,6 +32,8 @@ _CW340_TESTROM_PATH = _CW310_TESTROM_PATH
 
 _OTP_RMA_PATH = "{}/$(location {})".format(_PREFIX, _OTP_RMA)
 
+_FPGA_PATH_TMPL = "lowrisc_systems_{}_0.1/synth-vivado/{}"
+
 # Note: all of the targets are tagged with "manual" to prevent them from being
 # matched by bazel wildcards like "//...".  In order to build the bitstream,
 # you need to ask for it directly or by dependency via another rule, such as
@@ -51,10 +53,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310"],
     tags = ["manual"],
@@ -101,10 +103,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310_hyperdebug"],
     tags = ["manual"],
@@ -151,10 +153,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw340"],
     tags = ["manual"],