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[otbn,sim] Add simulator test cases for bignum vectorized instructions
This commit adds simple tests to test the simulator implementation of the vectorized instructions. Most of these tests are autogenerated when running a test using the generate_bn_simd_tests.py scripts. Signed-off-by: Pascal Etterli <[email protected]>
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hw/ip/otbn/doc/developing_otbn.md

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## Test the ISS
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The ISS has a simple test suite, which runs various instructions and
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makes sure they behave as expected. You can find the tests in
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`dv/otbnsim/test` and can run them with `make -C dv/otbnsim test`.
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makes sure they behave as expected.
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See the [simulator page](../dv/otbnsim/README.md) for more details.

hw/ip/otbn/dv/otbnsim/README.md

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To check correct behaviour, the two separate logs generated by the model and the RTL are compared.
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For more information about how OTBN RTL produces traces see the [Tracer README](../tracer/README.md).
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To see the C++ program that compares both traces, check the method `otbn_trace_checker.cc` in `../model/otbn_trace_entry`.
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## Testing the simulator
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There is a simple test suite to check the simulator implementation.
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It tests diverse instruction as defined by the tests in `./test/simple/` as well as some autogenerated tests for the bignum SIMD extension (see `generate_bn_simd_test.py`).
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All test can be run with `make test` (which also generates the SIMD tests) and a single test can be run using `pytest -vv -k <testname>.s`.
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# Ignore all autogenerated Bignum SIMD test programs
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bn-simd-generated/*
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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w10 = 0xbbaaaabbaaaabbaaccddeeccddeeccddeeccddeeccddeeccddeeccddeeccddee
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w11 = 0x3333ff3333ff3333ff3333ff3333ff33aabbaaaabbaaaabbaaaabbaaaabbaaaa
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w12 = 0x77557777557777557777557777557777557777557777557733ff3333ff3333ff
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INSN_CNT = 17
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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.section .text.start
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/*
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Load the vectors
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*/
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addi x2, x0, 0
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la x3, vecA
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bn.lid x2++, 0(x3)
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la x3, vecB
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bn.lid x2++, 0(x3)
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la x3, vecC
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bn.lid x2++, 0(x3)
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la x3, vecD
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bn.lid x2++, 0(x3)
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/* Pack the vectors */
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bn.pack w10, w1, w0, 64
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bn.pack w11, w2, w1, 128
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bn.pack w12, w3, w2, 192
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ecall
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.section .data
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/*
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Vectors to pack to 24-bit elements (FE byte should be ignored)
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VecA = 0xFECCDDEE_FECCDDEE_FECCDDEE_FECCDDEE_FECCDDEE_FECCDDEE_FECCDDEE_FECCDDEE
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VecB = 0xFEAABBAA_FEAABBAA_FEAABBAA_FEAABBAA_FEAABBAA_FEAABBAA_FEAABBAA_FEAABBAA
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VecC = 0xFE33FF33_FE33FF33_FE33FF33_FE33FF33_FE33FF33_FE33FF33_FE33FF33_FE33FF33
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VecD = 0xFE775577_FE775577_FE775577_FE775577_FE775577_FE775577_FE775577_FE775577
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WDR0, Bytes 0-23: Vector A (each element is CCDDEE)
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WDR0, Bytes 24-31: 1st part of vector B (each element is AABBAA)
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WDR1, Bytes 0-15: 2nd part of vector B
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WDR1, Bytes 16-31: 1st part of vector C (each element is 33FF33)
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WDR2, Bytes 0- 7: 2nd part of vector C
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WDR2, Bytes 8-31: Vector D (each element is 775577)
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Expected results
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WDR0 = 0xBBAA_AABBAA_AABBAA_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE
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0xBBAAAABBAAAABBAACCDDEECCDDEECCDDEECCDDEECCDDEECCDDEECCDDEECCDDEE
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WDR1 = 0x33_33FF33_33FF33_33FF33_33FF33_33FF33_AABBAA_AABBAA_AABBAA_AABBAA_AABBAA_AA
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0x3333FF3333FF3333FF3333FF3333FF33AABBAAAABBAAAABBAAAABBAAAABBAAAA
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WDR2 = 0x775577_775577_775577_775577_775577_775577_775577_775577_33FF33_33FF33_33FF
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0x77557777557777557777557777557777557777557777557733FF3333FF3333FF
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*/
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vecA:
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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.word 0xFECCDDEE
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vecB:
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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.word 0xFEAABBAA
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vecC:
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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.word 0xFE33FF33
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vecD:
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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.word 0xFE775577
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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w10 = 0x00ccddee00ccddee00ccddee00ccddee00ccddee00ccddee00ccddee00ccddee
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w11 = 0x00aabbaa00aabbaa00aabbaa00aabbaa00aabbaa00aabbaa00aabbaa00aabbaa
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w12 = 0x0033ff330033ff330033ff330033ff330033ff330033ff330033ff330033ff33
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w13 = 0x0077557700775577007755770077557700775577007755770077557700775577
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INSN_CNT = 15
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/* Copyright lowRISC contributors (OpenTitan project). */
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/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
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/* SPDX-License-Identifier: Apache-2.0 */
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.section .text.start
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/*
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Load the vectors
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*/
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addi x2, x0, 0
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la x3, vec1
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bn.lid x2++, 0(x3)
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la x3, vec2
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bn.lid x2++, 0(x3)
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la x3, vec3
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bn.lid x2++, 0(x3)
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/* Unpack the vectors */
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bn.unpk w10, w1, w0, 0
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bn.unpk w11, w1, w0, 192
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bn.unpk w12, w2, w1, 128
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bn.unpk w13, w2, w2, 64
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ecall
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.section .data
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/*
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Vectors to unpack 24-bit elements from
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WDR0, Bytes 0-23: Vector A (each element is CCDDEE)
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WDR0, Bytes 24-31: 1st part of vector B (each element is AABBAA)
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WDR1, Bytes 0-15: 2nd part of vector B
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WDR1, Bytes 16-31: 1st part of vector C (each element is 33FF33)
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WDR2, Bytes 0- 7: 2nd part of vector C
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WDR2, Bytes 8-31: Vector D (each element is 775577)
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WDR0 = 0xBBAA_AABBAA_AABBAA_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE_CCDDEE
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0xBBAAAABBAAAABBAACCDDEECCDDEECCDDEECCDDEECCDDEECCDDEECCDDEECCDDEE
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WDR1 = 0x33_33FF33_33FF33_33FF33_33FF33_33FF33_AABBAA_AABBAA_AABBAA_AABBAA_AABBAA_AA
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0x3333FF3333FF3333FF3333FF3333FF33AABBAAAABBAAAABBAAAABBAAAABBAAAA
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WDR2 = 0x775577_775577_775577_775577_775577_775577_775577_775577_33FF33_33FF33_33FF
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0x77557777557777557777557777557777557777557777557733FF3333FF3333FF
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Expected results
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VecA = 0x00CCDDEE_00CCDDEE_00CCDDEE_00CCDDEE_00CCDDEE_00CCDDEE_00CCDDEE_00CCDDEE
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VecB = 0x00AABBAA_00AABBAA_00AABBAA_00AABBAA_00AABBAA_00AABBAA_00AABBAA_00AABBAA
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VecC = 0x0033FF33_0033FF33_0033FF33_0033FF33_0033FF33_0033FF33_0033FF33_0033FF33
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VecD = 0x00775577_00775577_00775577_00775577_00775577_00775577_00775577_00775577
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*/
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vec1:
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.word 0xEECCDDEE
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.word 0xDDEECCDD
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.word 0xCCDDEECC
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.word 0xEECCDDEE
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.word 0xDDEECCDD
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.word 0xCCDDEECC
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.word 0xAAAABBAA
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.word 0xBBAAAABB
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vec2:
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.word 0xAABBAAAA
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.word 0xAAAABBAA
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.word 0xBBAAAABB
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.word 0xAABBAAAA
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.word 0x3333FF33
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.word 0xFF3333FF
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.word 0x33FF3333
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.word 0x3333FF33
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vec3:
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.word 0xFF3333FF
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.word 0x33FF3333
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.word 0x77775577
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.word 0x55777755
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.word 0x77557777
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.word 0x77775577
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.word 0x55777755
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.word 0x77557777

hw/ip/otbn/dv/otbnsim/test/simple_test.py

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from testutil import asm_and_link_one_file, SIM_DIR
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from shared.reg_dump import parse_reg_dump
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BN_SIMD_DIR_NAME = 'bn-simd-generated'
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BN_SIMD_GENERATOR_SCRIPT = 'generate_bn_simd_tests.py'
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def generate_bn_simd_tests() -> None:
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'''Generate most of the BN SIMD tests by calling the generator script.'''
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script_path = os.path.join(os.path.dirname(__file__), BN_SIMD_GENERATOR_SCRIPT)
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output_dir = os.path.join(os.path.dirname(__file__), 'simple', BN_SIMD_DIR_NAME)
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# Delete and re-create the output directory
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if os.path.exists(output_dir):
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subprocess.run(['rm', '-rf', output_dir], check=True)
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os.makedirs(output_dir)
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cmd = ['python3', script_path, '-o', output_dir]
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subprocess.run(cmd, check=True)
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def find_simple_tests() -> List[Tuple[str, str]]:
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'''Find all tests below ./simple (relative to this file)
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def pytest_generate_tests(metafunc: Any) -> None:
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if metafunc.function is test_count:
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generate_bn_simd_tests()
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tests = find_simple_tests()
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test_ids = [os.path.basename(e[0]) for e in tests]
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metafunc.parametrize("asm_file,expected_file", tests, ids=test_ids)

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