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[sw,otbn] Add KMAC interface to OTBNsim
Use the new KMAC OTBNsim model to extend OTBNsim. This commit adds new WSRs and CSRs to OTBNsim and connects them to the new KMAC model. Signed-off-by: Hakim Filali <[email protected]>
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‎hw/ip/otbn/README.md‎

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@@ -270,6 +270,103 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w
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Always reads as 0.
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</td>
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</tr>
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<tr>
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<td>0x7E0</td>
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<td>RW</td>
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<td>KMAC_STATUS</td>
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<td>
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Writes to this CSR are always ignored.
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This CSR exposes the internal state of the SHA3 FSM within KMAC.
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<br>
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Bit [ 0] SHA3_IDLE indicates whether the SHA3 core is in the idle state.
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Bit [ 1] SHA3_ABSORB indicates whether the SHA3 core is in the absorb state.
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Bit [ 2] SHA3_SQUEEZE indicates whether the SHA3 core is in the squeeze state.
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Bits [31:3] are reserved/ignored.
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</td>
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</tr>
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<tr>
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<td>0x7E1</td>
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<td>RW</td>
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<td>KMAC_IF_STATUS</td>
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<td>
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Write a 1 to bits 1 or 2 to clear the error bits.
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KMAC_IF_STATUS is a CSR that exposes status information for the OTBN-KMAC interface.
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<br>
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Bit [ 0] MSG_WRITE_RDY indicates whether the KMAC_DATA_S0/1 WSR is ready for the next word.
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Bit [ 1] MSG_SEND_ERROR indicates whether an error ocurred after issuing a message send command.
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Bit [ 2] MSG_WRITE_ERROR indicates whether an error ocurred after writing to the KMAC_DATA_S0/1 WSR.
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Bit [ 3] DIGEST_VALID0 indicates whether word 0 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 4] DIGEST_VALID1 indicates whether word 1 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 5] DIGEST_VALID2 indicates whether word 2 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 6] DIGEST_VALID3 indicates whether word 3 in the KMAC_DATA_S0/1 WSR is valid.
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Bits [31:7] are reserved/ignored.
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</td>
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</tr>
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<tr>
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<td>0x7E2</td>
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<td>RW</td>
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<td>KMAC_INTR</td>
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<td>
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Writing 1 to bit 0 of this register clears the interrupt.
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KMAC_INTR is a CSR that exposes a KMAC_ERROR interrupt of the KMAC HW IP.
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<br>
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Bit [ 0] KMAC_ERROR indicates whether an error ocurred in the KMAC HW IP.
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Bits [31:1] are reserved/ignored.
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</td>
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</tr>
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<tr>
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<td>0x7E3</td>
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<td>RW</td>
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<td>KMAC_ERROR</td>
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<td>
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Writes to this register are ignored.
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This register exposes information from the KMAC HW IP ERR_CODE register.
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</td>
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</tr>
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<tr>
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<td>0x7E4</td>
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<td>RW</td>
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<td>KMAC_CFG</td>
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<td>
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This register allows OTBN to set the KMAC hashing mode (mode = SHAKE / cSHAKE / SHA3), enable or disable keyed KMAC mode (kmac_en = 0/1), and select the desired security strength (kstrength = L128 / L224 / L256 / L384 / L512).
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Reading from this register returns the current KMAC configuration.
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<br>
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Bit [ 0] KMAC_EN enables keyed operation in the KMAC HWIP.
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Bits [ 3:1] STRENGTH is the KAMC security strength.
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Bits [ 5:4] MODE is the KMAC hashing mode.
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Bits [31:6] are reserved/ignored.
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</td>
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</tr>
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<tr>
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<td>0x7E5</td>
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<td>RW</td>
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<td>KMAC_MSG_SEND</td>
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<td>
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This CSR consists of a single bit that, if set to one, will trigger OTBN to send the contents of KMAC_DATA_S0 and KMAC_DATA_S1 to KMAC.
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Reads from this register always return a 0.
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</td>
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</tr>
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<tr>
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<td>0x7E6</td>
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<td>RW</td>
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<td>KMAC_CMD</td>
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<td>
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The register allows OTBN to issue START, PROCESS, RUN and DONE commands to KMAC.
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Reads from this register always return a 0.
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<br>
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Bit [ 5:0] CMD is the KMAC command field.
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Bits [31:6] are reserved/ignored.
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</td>
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</tr>
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<tr>
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<td>0x7E7</td>
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<td>RW</td>
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<td>KMAC_BYTE_STROBE</td>
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<td>
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BYTE_STROBE is a CSR that specifies which input bytes of KMAC_DATA are valid and should be consumed by KMAC.
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Reads from this register return the current configuration of the KMAC_BYTE_STROBE CSR.
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</td>
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</tr>
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<tr>
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<td>0xFC0</td>
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<td>RO</td>
@@ -422,6 +519,24 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w
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A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key.
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</td>
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</tr>
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<tr>
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<td>0x8</td>
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<td>RW</td>
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<td><a name="kmac-data-s0">KMAC_DATA_S0</a></td>
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<td>
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KMAC_DATA_S0 is used by OTBN to provide masked input message shares to KMAC and to retrieve masked digest shares.
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This WSR is 256 bits wide and holds one share of the message or digest.
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</td>
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</tr>
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<tr>
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<td>0x9</td>
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<td>RW</td>
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<td><a name="kmac-data-s1">KMAC_DATA_S1</a></td>
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<td>
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KMAC_DATA_S1 is used by OTBN to provide masked input message shares to KMAC and to retrieve masked digest shares.
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This WSR is 256 bits wide and holds one share of the message or digest.
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</td>
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</tr>
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</tbody>
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</table>
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‎hw/ip/otbn/data/csr.yml‎

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Write to this CSR to begin a request to fill the RND cache.
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Always reads as 0.
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- name: kmac_status
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address: 0x7e0
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doc: |
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Writes to this CSR are always ignored.
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This CSR exposes the internal state of the SHA3 FSM within KMAC.
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Bit [ 0] SHA3_IDLE indicates whether the SHA3 core is in the idle state.
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Bit [ 1] SHA3_ABSORB indicates whether the SHA3 core is in the absorb state.
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Bit [ 2] SHA3_SQUEEZE indicates whether the SHA3 core is in the squeeze state.
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Bits [31:3] are reserved/ignored.
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- name: kmac_if_status
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address: 0x7e1
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doc: |
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Write a 1 to bits 1 or 2 to clear the error bits.
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KMAC_IF_STATUS is a CSR that exposes status information for the OTBN-KMAC interface.
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Bit [ 0] MSG_WRITE_RDY indicates whether the KMAC_DATA_S0/1 WSR is ready for the next word.
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Bit [ 1] MSG_SEND_ERROR indicates whether an error ocurred after issuing a message send command.
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Bit [ 2] MSG_WRITE_ERROR indicates whether an error ocurred after writing to the KMAC_DATA_S0/1 WSR.
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Bit [ 3] DIGEST_VALID0 indicates whether word 0 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 4] DIGEST_VALID1 indicates whether word 1 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 5] DIGEST_VALID2 indicates whether word 2 in the KMAC_DATA_S0/1 WSR is valid.
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Bit [ 6] DIGEST_VALID3 indicates whether word 3 in the KMAC_DATA_S0/1 WSR is valid.
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Bits [31:7] are reserved/ignored.
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- name: kmac_intr
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address: 0x7e2
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doc: |
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Writing 1 to bit 0 of this register clears the interrupt.
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KMAC_INTR is a CSR that exposes a KMAC_ERROR interrupt of the KMAC HW IP.
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Bit [ 0] KMAC_ERROR indicates whether an error ocurred in the KMAC HW IP.
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Bits [31:1] are reserved/ignored.
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- name: kmac_error
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address: 0x7e3
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doc: |
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Writes to this register are ignored.
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This register exposes information from the KMAC HW IP ERR_CODE register.
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- name: kmac_cfg
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address: 0x7e4
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doc: |
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This register allows OTBN to set the KMAC hashing mode (mode = SHAKE / cSHAKE / SHA3), enable or disable keyed KMAC mode (kmac_en = 0/1), and select the desired security strength (kstrength = L128 / L224 / L256 / L384 / L512).
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Reading from this register returns the current KMAC configuration.
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Bit [ 0] KMAC_EN enables keyed operation in the KMAC HWIP.
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Bits [ 3:1] STRENGTH is the KAMC security strength.
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Bits [ 5:4] MODE is the KMAC hashing mode.
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Bits [31:6] are reserved/ignored.
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- name: kmac_msg_send
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address: 0x7e5
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doc: |
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This CSR consists of a single bit that, if set to one, will trigger OTBN to send the contents of KMAC_DATA_S0 and KMAC_DATA_S1 to KMAC.
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Reads from this register always return a 0.
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- name: kmac_cmd
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address: 0x7e6
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doc: |
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The register allows OTBN to issue START, PROCESS, RUN and DONE commands to KMAC.
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Reads from this register always return a 0.
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Bit [ 5:0] CMD is the KMAC command field.
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Bits [31:6] are reserved/ignored.
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- name: kmac_byte_strobe
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address: 0x7e7
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doc: |
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BYTE_STROBE is a CSR that specifies which input bytes of KMAC_DATA are valid and should be consumed by KMAC.
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Reads from this register return the current configuration of the KMAC_BYTE_STROBE CSR.
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- name: rnd
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address: 0xfc0
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read-only: true

‎hw/ip/otbn/data/wsr.yml‎

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Bits [127:0] contain bits [383:256] of share 1 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md).
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A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key.
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- name: kmac_data_s0
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address: 8
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doc: |
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KMAC_DATA_S0 is used by OTBN to provide masked input message shares to KMAC and to retrieve masked digest shares.
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This WSR is 256 bits wide and holds one share of the message or digest.
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- name: kmac_data_s1
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address: 9
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doc: |
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KMAC_DATA_S1 is used by OTBN to provide masked input message shares to KMAC and to retrieve masked digest shares.
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This WSR is 256 bits wide and holds one share of the message or digest.

‎hw/ip/otbn/dv/otbnsim/sim/BUILD‎

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@@ -17,6 +17,7 @@ py_library(
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srcs = ["csr.py"],
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deps = [
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":flags",
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":kmac",
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":wsr",
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],
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":ext_regs",
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":flags",
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":gpr",
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":kmac",
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":loop",
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":reg",
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":trace",
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srcs = ["wsr.py"],
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deps = [
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":ext_regs",
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":kmac",
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":trace",
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],
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)

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