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hw/ip/uart/doc/theory_of_operation.md
@@ -70,7 +70,7 @@ detected as high and the optional parity bit is correct the data byte
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is pushed into a 32 byte deep RX FIFO. The data can be read out by
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reading [`RDATA`](registers.md#rdata) register.
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-This behaviour of the receiver can be used to compute the approximate
+This behavior of the receiver can be used to compute the approximate
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baud clock frequency error that can be tolerated between the
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transmitter at the other end of the cable and the receiver. The
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initial sample point is aligned with the center of the START bit. The
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