[ast] split ast os to power domains

Author: Eran Meisner

hw/top_earlgrey/dv/env/ast_ext_clk_if.sv

@@ -15,19 +15,19 @@ interface ast_ext_clk_if ();
   // This task returns once the external clock has gone through an active cycle.
   // Notice it will fail if the active cycle has already started.
   task automatic span_external_clock_active_window();
-    `DV_WAIT(u_ast.u_ast_clks_byp.u_io_clk_byp_en.out_o == 1'b1,
+    `DV_WAIT(u_ast.u_ast_main.u_ast_clks_byp_main.u_io_clk_byp_en.out_o == 1'b1,
                  "Took too long to enable external clock", WaitForExctClkSelChangeInNs,
                  "ast_ext_clk_if")
     `uvm_info("ast_ext_clk_if", "External clk became active for io clk", UVM_MEDIUM)
-    `DV_WAIT(u_ast.u_ast_clks_byp.u_io_clk_byp_en.out_o == 1'b0,
+    `DV_WAIT(u_ast.u_ast_main.u_ast_clks_byp_main.u_io_clk_byp_en.out_o == 1'b0,
                  "Took too long to disable external clock", WaitForExctClkSelChangeInNs,
                  "ast_ext_clk_if")
     `uvm_info("ast_ext_clk_if", "External clk back to inactive for io clk", UVM_MEDIUM)
   endtask
 
   // Returns 1 if the external clock is in use.
   function automatic logic is_ext_clk_in_use();
-    return u_ast.u_ast_clks_byp.u_io_clk_byp_en.out_o;
+    return u_ast.u_ast_main.u_ast_clks_byp_main.u_io_clk_byp_en.out_o;
   endfunction
 
 endinterface : ast_ext_clk_if

hw/top_earlgrey/dv/env/ast_supply_if.sv

@@ -36,7 +36,7 @@ interface ast_supply_if (
   localparam int MioInSysrstCtrlAonKey0In = 46;
 
   function static void force_vcaon_pok(bit value);
-    force u_ast.u_rglts_pdm_3p3v.vcaon_pok_h_o = value;
+    force u_ast.u_ast_aon.u_rglts_pdm_3p3v.vcaon_pok_h_o = value;
   endfunction
 
   // Create glitch in vcaon_pok_h_o some cycles after this is invoked. Hold vcaon_pok_h_o low for

hw/top_earlgrey/dv/env/chip_if.sv

@@ -40,7 +40,7 @@ interface chip_if;
 `define AES_CONTROL_HIER    `AES_HIER.u_aes_core.u_aes_control
 `define ALERT_HANDLER_HIER  `TOP_HIER.u_alert_handler
 `define AON_TIMER_HIER      `TOP_HIER.u_aon_timer_aon
-`define AST_HIER            u_ast
+`define AST_HIER            u_ast.u_ast_aon
 `define CLKMGR_HIER         `TOP_HIER.u_clkmgr_aon
 `define CPU_HIER            `TOP_HIER.u_rv_core_ibex
 `define CPU_CORE_HIER       `CPU_HIER.u_core

hw/top_earlgrey/dv/env/seq_lib/chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq.sv

@@ -7,9 +7,9 @@ class chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq extends chip_sw_base_vseq;
 
   `uvm_object_new
 
-  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.adc_d_o[9:0]";
-  localparam string ADC_DATA_VALID = "tb.dut.u_ast.adc_d_val_o";
-  localparam string ADC_POWERDOWN = "tb.dut.u_ast.adc_pd_i";
+  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.u_ast_aon.adc_d_o[9:0]";
+  localparam string ADC_DATA_VALID = "tb.dut.u_ast.u_ast_aon.adc_d_val_o";
+  localparam string ADC_POWERDOWN = "tb.dut.u_ast.u_ast_aon.adc_pd_i";
 
   localparam string ADC_CTRL_WAKEUP_REQ = "tb.dut.top_earlgrey.u_pwrmgr_aon.wakeups_i[1]";
 

hw/top_earlgrey/dv/env/seq_lib/chip_sw_ast_clk_rst_inputs_vseq.sv

@@ -7,11 +7,11 @@ class chip_sw_ast_clk_rst_inputs_vseq extends chip_sw_base_vseq;
 
   `uvm_object_new
 
-  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.adc_d_o[9:0]";
-  localparam string ADC_CHANNEL_IN_SEL_HDL_PATH = "tb.dut.u_ast.adc_chnsel_i[1:0]";
+  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.u_ast_aon.adc_d_o[9:0]";
+  localparam string ADC_CHANNEL_IN_SEL_HDL_PATH = "tb.dut.u_ast.u_ast_aon.adc_chnsel_i[1:0]";
 
-  localparam string ADC_DATA_VALID = "tb.dut.u_ast.adc_d_val_o";
-  localparam string ADC_POWERDOWN = "tb.dut.u_ast.adc_pd_i";
+  localparam string ADC_DATA_VALID = "tb.dut.u_ast.u_ast_aon.adc_d_val_o";
+  localparam string ADC_POWERDOWN = "tb.dut.u_ast.u_ast_aon.adc_pd_i";
   localparam string ADC_CTRL_WAKEUP_REQ = "tb.dut.top_earlgrey.u_pwrmgr_aon.wakeups_i[1]";
   localparam uint NUM_ADC_CHANNELS = 2;
   localparam uint NUM_LOW_POWER_SAMPLES = 3;

hw/top_earlgrey/dv/env/seq_lib/chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq.sv

@@ -6,8 +6,8 @@ class chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq extends chip_sw_base_vseq;
   `uvm_object_utils(chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq)
   `uvm_object_new
 
-  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.adc_d_o[9:0]";
-  localparam string ADC_CHANNEL_IN_SEL_HDL_PATH = "tb.dut.u_ast.adc_chnsel_i[1:0]";
+  localparam string ADC_CHANNEL_OUT_HDL_PATH = "tb.dut.u_ast.u_ast_aon.adc_d_o[9:0]";
+  localparam string ADC_CHANNEL_IN_SEL_HDL_PATH = "tb.dut.u_ast.u_ast_aon.adc_chnsel_i[1:0]";
 
   event adc_valid_rising_edge_event;
   event adc_channel1_event;

hw/top_earlgrey/ip/ast/ast.core

@@ -2,14 +2,13 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_ast:0.1"
+name: "lowrisc:systems:ast:0.1"
 description: "Analog Sensor Top generic views"
-
 filesets:
   files_rtl:
     depend:
       - lowrisc:ip:tlul
-      - lowrisc:prim:all
+      - lowrisc:prim_generic:all
       - lowrisc:prim:clock_buf
       - lowrisc:prim:clock_div
       - lowrisc:prim:clock_gating
@@ -18,20 +17,23 @@ filesets:
       - lowrisc:prim:lfsr
       - lowrisc:earlgrey_ip:pinmux_pkg
       - lowrisc:prim:assert
+      - lowrisc:prim:prim_pkg
       - lowrisc:prim:mubi
       - lowrisc:prim:multibit_sync
-      - lowrisc:prim:multibit_sync
       - lowrisc:ip:lc_ctrl_pkg
       - lowrisc:ip:edn_pkg
       - lowrisc:earlgrey_ip:alert_handler_pkg
       - lowrisc:earlgrey_ip:clkmgr_pkg
       - lowrisc:earlgrey_ip:rstmgr_pkg
       - lowrisc:systems:top_earlgrey_ast_pkg
-      - lowrisc:prim:prim_pkg
     files:
       - rtl/ast_reg_pkg.sv
+      - rtl/ast_pkg.sv
       - rtl/ast_bhv_pkg.sv
+      - rtl/ast_aon_main_pkg.sv
       - rtl/ast.sv
+      - rtl/ast_aon.sv
+      - rtl/ast_main.sv
       - rtl/ast_reg_top.sv
       - rtl/adc.sv
       - rtl/adc_ana.sv
@@ -49,7 +51,8 @@ filesets:
       - rtl/usb_clk.sv
       - rtl/usb_osc.sv
       - rtl/gfr_clk_mux2.sv
-      - rtl/ast_clks_byp.sv
+      - rtl/ast_clks_byp_aon.sv
+      - rtl/ast_clks_byp_main.sv
       - rtl/rglts_pdm_3p3v.sv
       - rtl/ast_pulse_sync.sv
       - rtl/ast_entropy.sv
@@ -127,5 +130,5 @@ targets:
       - files_rtl
     tools:
       vcs:
-        vcs_options: [-sverilog -ntb_opts uvm-1.2 -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++17 -timescale=1ns/1ps -l vcs.log]
+        vcs_options: [-sverilog -ntb_opts uvm-1.2 -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++11 -timescale=1ns/1ps -l vcs.log]
     toplevel: ast

hw/top_earlgrey/ip/ast/ast_pkg.core

@@ -2,15 +2,13 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_ast_pkg"
+name: "lowrisc:systems:ast_pkg"
 description: "Analog sensor top (AST) wrapper package"
-virtual:
-  - lowrisc:systems:ast_pkg
 
 filesets:
   files_rtl:
     depend:
-      - lowrisc:earlgrey_constants:top_pkg
+      - lowrisc:constants:top_pkg
       - lowrisc:ip:lc_ctrl_pkg
     files:
       - rtl/ast_pkg.sv

hw/top_earlgrey/ip/ast/rtl/adc.sv

@@ -17,7 +17,7 @@ module adc #(
 ) (
   input ast_pkg::awire_t adc_a0_ai,  // ADC A0 Analog Input
   input ast_pkg::awire_t adc_a1_ai,  // ADC A1 Analog Input
-  input [AdcChannels-1:0] adc_chnsel_i,  // Onehot value only for selection
+  input [AdcChannels-1:0] adc_chnsel_i,  // Onehot value only for selrction
   input adc_pd_i,                    // ADC Power Down
   input clk_adc_i,                   // ADC Clock (aon_clk - 200KHz)
   input rst_adc_ni,                  // ADC Reset active low
@@ -54,7 +54,7 @@ always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin
   end
 end
 
-// New Conversion
+// New Convertion
 assign new_convert = chn_selected && !chn_selected_d && !adc_busy;
 
 ////////////////////////////////////////