[cov] Apply asm auto-instrumentation

sasdf · sasdf · commit bcd24966692e · 2026-01-29T13:04:45.000+08:00
Reruns the assembly auto-instrumentation tool to generate
the coverage markers for newly enabled asm targets.

```
bash util/coverage/asm/run_instrument.sh --apply
```

Change-Id: I69d8e43713fc62a9f3274e95e0302aa881e12e1b
Signed-off-by: Yi-Hsuan Deng &lt;yhdeng@google.com&gt;
diff --git a/sw/device/silicon_creator/lib/flash_exc_handler.S b/sw/device/silicon_creator/lib/flash_exc_handler.S
@@ -95,22 +95,26 @@ flash_exception_handler:
   // PRAGMA_COVERAGE: autogen start
 
   // Get the mcause, mask the reason and check that it is LoadAccessFault.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,1)
   csrr a1, mcause
   andi a1, a1, 31
   li   a2, LOAD_ACCESS_FAULT
   bne  a1, a2, .L_not_a_flash_error
 
   // Check if there is a flash error.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,2)
   li   a3, TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR
   lw   a1, FLASH_CTRL_FAULT_STATUS_REG_OFFSET(a3)
   andi a1, a1, PHY_ERRORS
   beqz a1, .L_not_a_flash_error
 
   // Clear the flash error.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,3)
   sw   x0, FLASH_CTRL_FAULT_STATUS_REG_OFFSET(a3)
   // Hardening: check that the error is cleared.
   lw   a1, FLASH_CTRL_FAULT_STATUS_REG_OFFSET(a3)
   beqz a1, .L_flash_fault_handled
+  COVERAGE_ASM_AUTOGEN_MARK(t6,4)
   j    .L_not_a_flash_error
   unimp
   unimp
@@ -140,6 +144,7 @@ flash_exception_handler:
   // Where rd' and rs1' are (register_num - 8, ie: rd' of 0 means reg x8).
   //
 
+  COVERAGE_ASM_AUTOGEN_MARK(t6,5)
   csrr a0, mepc
   lh   a2, 0(a0)
   addi a0, a0, OT_HALF_WORD_SIZE
@@ -149,10 +154,12 @@ flash_exception_handler:
   bne  a3, a1, .L_compressed_trap_instr
   // Check if its an uncompressed load instruction by checking that the next
   // five bits are zero.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,6)
   srli a3, a2, 2
   andi a3, a3, 0x1f
   bnez a3, .L_not_a_flash_error
   // Get the register number into a3 by masking off the rd field.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,7)
   srli a3, a2, 7
   andi a3, a3, 0x1f
   // We already added one half word, so for a 32-bit instruction, add another.
@@ -161,15 +168,18 @@ flash_exception_handler:
 
 .L_compressed_trap_instr:
   // Check if its a compressed load instruction.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,8)
   bnez a3, .L_not_a_flash_error
   // Get the register number into a3 by masking off the rd' field and adding 8.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,9)
   srli a3, a2, 2
   andi a3, a3, 7
   addi a3, a3, 8
 
 .L_hardened_mepc_check:
   // Hardening: double-check that the retval calculation is 4 bytes or fewer
   // from the original value of MEPC.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,10)
   addi a1, a1, 1
   csrr a2, mepc
   sub  a2, a0, a2
@@ -179,9 +189,11 @@ flash_exception_handler:
   // that register.
   // RISCV register x0, aka zero.  This register is always const 0, so there
   // is nothing to do.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,11)
   beqz a3, .L_flash_fault_done
 
   // All other registers load the value 0xFFFFFFFF as the faulting value.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,12)
   li   a2, -1
   slli a3, a3, 2
   add  a3, a3, sp
@@ -190,6 +202,7 @@ flash_exception_handler:
 .L_flash_fault_done:
   // Exception handler exit and return to C:
   // Load the correct MEPC for the next instruction in the current task.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,13)
   csrw mepc, a0
 
   // Restore all registers from the stack and restore SP to its former value.
@@ -239,6 +252,7 @@ flash_exception_handler:
   // Note: we _also_ do not restore SP - we'll restart the stack at
   // `ram_end - 128`.  This allows us to report exceptions after jumping
   // to the next stage if the next stage has trashed its SP register.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,15)
   j INTERRUPT_HANDLER
   unimp
   .size flash_exception_handler, .-flash_exception_handler
diff --git a/sw/device/silicon_creator/rom/rom_epmp_init.S b/sw/device/silicon_creator/rom/rom_epmp_init.S
@@ -61,6 +61,7 @@ rom_epmp_init:
   // Setup PMP address registers.
 
   // ROM TEXT
+  COVERAGE_ASM_AUTOGEN_MARK(t6,0)
   la   t0, _epmp_text_tor_lo
   csrw pmpaddr0, t0
   la   t0, _epmp_text_tor_hi
diff --git a/sw/device/silicon_creator/rom/rom_start.S b/sw/device/silicon_creator/rom/rom_start.S
@@ -160,18 +160,21 @@ _rom_start_boot:
 
 LABEL_FOR_TEST(kRomStartBootMaybeHalt)
   // Check if we should halt here.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,0)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_OFFSET(a0)
   bnez t0, .L_exec_en
 LABEL_FOR_TEST(kRomStartBootHalted)
 .L_halt_loop:
+  COVERAGE_ASM_AUTOGEN_MARK(t6,1)
   wfi
   j .L_halt_loop
 
 LABEL_FOR_TEST(kRomStartBootExecEn)
 .L_exec_en:
   // Enable NMIs from the watchdog timer.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,2)
   li t0, TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR
   li t1, (1 << RV_CORE_IBEX_NMI_ENABLE_WDOG_EN_BIT)
   sw t1, RV_CORE_IBEX_NMI_ENABLE_REG_OFFSET(t0)
@@ -194,6 +197,7 @@ LABEL_FOR_TEST(kRomStartBootExecEn)
   beq t0, t1, .L_skip_watchdog_init
 
   // Configure the watchdog's bark and bite thresholds.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,3)
   li t0, TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR
   li t1, WDOG_BARK_THOLD
   sw t1, AON_TIMER_WDOG_BARK_THOLD_REG_OFFSET(t0)
@@ -207,6 +211,7 @@ LABEL_FOR_TEST(kRomStartStoreT1ToBiteThold)
 .L_skip_watchdog_init:
 
   // Configure rstmgr alert and cpu info collection.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,4)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET(a0)
@@ -215,20 +220,24 @@ LABEL_FOR_TEST(kRomStartStoreT1ToBiteThold)
   // Enable alert info collection if enabled in OTP.
   andi t2, t0, 0xff
   bne  t2, t1, .L_skip_rstmgr_alert_info_en
+  COVERAGE_ASM_AUTOGEN_MARK(t6,5)
   li   t2, (1 << RSTMGR_ALERT_INFO_CTRL_EN_BIT)
   sw   t2,  RSTMGR_ALERT_INFO_CTRL_REG_OFFSET(a0)
 .L_skip_rstmgr_alert_info_en:
   // Enable cpu info collection if enabled in OTP.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,6)
   srli t0, t0, 8
   andi t2, t0, 0xff
   bne  t2, t1, .L_skip_rstmgr_cpu_info_en
+  COVERAGE_ASM_AUTOGEN_MARK(t6,7)
   li   t2, (1 << RSTMGR_CPU_INFO_CTRL_EN_BIT)
   sw   t2,  RSTMGR_ALERT_INFO_CTRL_REG_OFFSET(a0)
 .L_skip_rstmgr_cpu_info_en:
 
 LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // Clear all the machine-defined interrupts, `MEIE`, `MTIE`, and `MSIE` fields
   // of `mie`.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,8)
   li   t0, 0x00000888
   csrc mie, t0
 
@@ -240,6 +249,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   bne  t0, t1, .L_ast_init_end
 
   // Copy the AST configuration from OTP.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,9)
   li   a0, (TOP_EARLGREY_AST_BASE_ADDR)
   li   a1, (TOP_EARLGREY_AST_BASE_ADDR + AST_REGAL_REG_OFFSET + 4)
   li   a2, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
@@ -250,11 +260,13 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // Enable jittery clock if not strictly disabled in OTP.
   // Use hardcoded MULTIBIT_ASM_BOOL4_TRUE as the enable word to reduce all
   // other possible OTP values to true.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,10)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET(a0)
   li   t1, MULTIBIT_ASM_BOOL4_FALSE
   beq  t0, t1, .L_ast_init_end
+  COVERAGE_ASM_AUTOGEN_MARK(t6,11)
   li   a0, TOP_EARLGREY_CLKMGR_AON_BASE_ADDR
   li   t1, MULTIBIT_ASM_BOOL4_TRUE
   sw   t1, CLKMGR_JITTER_ENABLE_REG_OFFSET(a0)
@@ -264,16 +276,19 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // CREATOR_SW_CFG_RMA_SPIN_CYCLES to let the transition start and continue
   // looping while lc_ctrl is not ready. Reset if the CPU is still executing at
   // the end.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,12)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET(a0)
   li   t6, HARDENED_BOOL_TRUE
   bne  t0, t6, .L_rma_spin_skip
 
+  COVERAGE_ASM_AUTOGEN_MARK(t6,13)
   li   a1, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t1, OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET(a1)
   beq  t1, t6, .L_rma_spin_check_straps
+  COVERAGE_ASM_AUTOGEN_MARK(t6,14)
   unimp
   unimp
   unimp
@@ -289,6 +304,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // |------------------+----------------+----------------+------------------|
   // | Configuration:   | Input          | Input          | Input            |
   // |                  | Pull-down      | Pull-down      | Pull-up          |
+  COVERAGE_ASM_AUTOGEN_MARK(t6,15)
   li   a0, (TOP_EARLGREY_PINMUX_AON_BASE_ADDR + \
             PINMUX_MIO_PAD_ATTR_0_REG_OFFSET)
   li   t0, (1 << PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT) | \
@@ -312,10 +328,12 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   csrw mcycle, zero
   li   t0, PINMUX_PAD_ATTR_PROP_CYCLES
 .L_rma_strap_pu_spin_cycles_loop:
+  COVERAGE_ASM_AUTOGEN_MARK(t6,16)
   csrr t1, mcycle
   bltu t1, t0, .L_rma_strap_pu_spin_cycles_loop
 
   // Read the strap GPIOs and check their value.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,17)
   li   a0, TOP_EARLGREY_GPIO_BASE_ADDR
   lw   t0, GPIO_DATA_IN_REG_OFFSET(a0)
   li   t5, SW_STRAP_MASK
@@ -325,12 +343,14 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   bne  t0, t6, .L_rma_spin_skip
 
   // Double-check the GPIO strap value.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,18)
   li   t6, HARDENED_BOOL_TRUE
   li   a1, TOP_EARLGREY_GPIO_BASE_ADDR
   lw   t1, GPIO_DATA_IN_REG_OFFSET(a1)
   and  t1, t1, t5
   xor  t1, t1, t4
   beq  t1, t6, .L_rma_spin_init
+  COVERAGE_ASM_AUTOGEN_MARK(t6,19)
   unimp
   unimp
   unimp
@@ -340,20 +360,24 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // the lifecycle transition request on JTAG.  Since this is a wait
   // loop, disable the watchdog.
 .L_rma_spin_init:
+  COVERAGE_ASM_AUTOGEN_MARK(t6,20)
   csrw mcycle, zero
   li   a0, TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR
   sw   zero, AON_TIMER_WDOG_CTRL_REG_OFFSET(a0)
 .L_rma_spin_cycles_loop:
+  COVERAGE_ASM_AUTOGEN_MARK(t6,21)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_OFFSET(a0)
   csrr t1, mcycle
   bltu t1, t0, .L_rma_spin_cycles_loop
 .L_rma_spin_lc_ctrl_loop:
+  COVERAGE_ASM_AUTOGEN_MARK(t6,22)
   li   a0, TOP_EARLGREY_LC_CTRL_BASE_ADDR
   lw   t0, LC_CTRL_STATUS_REG_OFFSET(a0)
   andi t0, t0, (1 << LC_CTRL_STATUS_READY_BIT)
   beqz t0, .L_rma_spin_lc_ctrl_loop
+  COVERAGE_ASM_AUTOGEN_MARK(t6,23)
   unimp
   unimp
   unimp
@@ -363,12 +387,14 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   // Skip the `entropy_src` health checks configuration if the
   // `RNG_HEALTH_CONFIG_DIGEST` is not programmed. The default digest value is
   // 0 given that it is stored in a software OTP partition.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,24)
   li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_OFFSET(a0)
   beqz t0, .L_entropy_enable
 
   // Copy the entropy source health checks configuration thresholds from OTP.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,25)
   li   a0, (TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + \
             ENTROPY_SRC_REPCNT_THRESHOLDS_REG_OFFSET)
   li   a1, (TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + \
@@ -379,6 +405,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   call crt_section_copy
 
   // Configure the entropy source health alert threshold.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,26)
   li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
   li a1, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
@@ -388,6 +415,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
 .L_entropy_enable:
   // The following sequence enables the minimum level of entropy required to
   // initialize memory scrambling, as well as the entropy distribution network.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,27)
   li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
 
   // Note for BOOT_ROM initialization the FIPS_ENABLE bit is set to kMultiBitBool4False
@@ -428,6 +456,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_OFFSET(a0)
   li   t1, HARDENED_BOOL_FALSE
   beq t0, t1, .L_sram_key_renew_skip
+  COVERAGE_ASM_AUTOGEN_MARK(t6,28)
   COVERAGE_ASM_BACKUP_COUNTERS(s10, s11)
   li a0, TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR
   li a1, (1 << SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT) | (1 << SRAM_CTRL_CTRL_INIT_BIT)
@@ -486,6 +515,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
    */
 
   // Initialize the `.bss` section.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,30)
   la   a0, _bss_start
   la   a1, _bss_end
   call crt_section_clear
@@ -497,6 +527,7 @@ LABEL_FOR_TEST(kRomStartWatchdogEnabled)
   //
   // If an exception fires, the handler is conventionally only allowed to clobber
   // memory at addresses below `sp`.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,31)
   la sp, _stack_end
 
   // PRAGMA_COVERAGE: skip start
diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_start.S b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_start.S
@@ -54,6 +54,7 @@ _imm_section_start_boot:
    */
 
   // Clear `MIE` field of `mstatus` (disable interrupts globally).
+  COVERAGE_ASM_AUTOGEN_MARK(t6,0)
   csrci mstatus, 0x8
 
   /**
@@ -80,13 +81,15 @@ _imm_section_start_boot:
    * We do this despite zeroing all of SRAM above, so that we still zero `.bss`
    * once we've enabled SRAM scrambling.
    */
+  COVERAGE_ASM_AUTOGEN_MARK(t6,1)
   la   a0, _bss_start
   la   a1, _bss_end
   jal  ra, crt_section_clear
 
   /**
    * Restore registers.
    */
+  COVERAGE_ASM_AUTOGEN_MARK(t6,2)
   lw ra, 4(sp)
   addi sp, sp, 8
 
diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_start.S b/sw/device/silicon_creator/rom_ext/rom_ext_start.S
@@ -160,6 +160,7 @@ _rom_ext_start_boot:
   /**
    * Initialize the `.data` section in RAM from ROM.
    */
+  COVERAGE_ASM_AUTOGEN_MARK(t6,2)
   la   a0, _data_start
   la   a1, _data_end
   la   a2, _data_init_start
@@ -171,11 +172,13 @@ _rom_ext_start_boot:
    * We do this despite zeroing all of SRAM above, so that we still zero `.bss`
    * once we've enabled SRAM scrambling.
    */
+  COVERAGE_ASM_AUTOGEN_MARK(t6,3)
   la   a0, _bss_start
   la   a1, _bss_end
   call crt_section_clear
 
   // Re-clobber all of the temporary registers.
+  COVERAGE_ASM_AUTOGEN_MARK(t6,4)
   li t0, 0x0
   li t1, 0x0
   li t2, 0x0
